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W3EG7265S262JD3M

Description
DDR DRAM, 64MX72, 0.75ns, CMOS, DIMM-184
File Size196KB,12 Pages
ManufacturerMicrosemi
Websitehttps://www.microsemi.com
Download Datasheet Parametric View All

W3EG7265S262JD3M Overview

DDR DRAM, 64MX72, 0.75ns, CMOS, DIMM-184

W3EG7265S262JD3M Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
Objectid1650366338
package instructionDIMM,
Reach Compliance Codeunknown
access modeDUAL BANK PAGE BURST
Maximum access time0.75 ns
Other featuresAUTO/SELF REFRESH
JESD-30 codeR-XDMA-N184
memory density4831838208 bit
Memory IC TypeDDR DRAM
memory width72
Number of functions1
Number of ports1
Number of terminals184
word count67108864 words
character code64000000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize64MX72
Package body materialUNSPECIFIED
encapsulated codeDIMM
Package shapeRECTANGULAR
Package formMICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
self refreshYES
Maximum supply voltage (Vsup)2.7 V
Minimum supply voltage (Vsup)2.3 V
Nominal supply voltage (Vsup)2.5 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formNO LEAD
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
White Electronic Designs
W3EG7265S-JD3
PRELIMINARY*
512MB – 2x32Mx72 DDR SDRAM REGISTERED, w/PLL
FEATURES
Double-data-rate architecture
DDR200 and DDR266
• JEDEC design specificaitons
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2,5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh
Serial presence detect
Dual Rank
Power Supply: 2.5V ± 0.2V
JEDEC standard 184 pin DIMM package
• PCB height: 30.48mm (1.20")
NOTE: Consult factory for availability of:
• RoHS compliant products
• Vendor source control options
• Industrial temperature option
* This product is under development, is not qualified or characterized and is subject to
change without notice.
DESCRIPTION
The W3EG7265S is a 2x32Mx72 Double Data Rate
SDRAM memory module based on 256Mb DDR SDRAM
components. The module consists of eighteen 32Mx8 DDR
SDRAMs in 66 pin TSOP package mounted on a 184 Pin
FR4 substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lenths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
OPERATING FREQUENCIES
DDR266 @CL=2
Clock Speed
CL-t
RCD
-t
RP
133MHz
2-2-2
DDR266 @CL=2.5
133MHz
2.5-3-3
DDR200 @CL=2
100MHz
2-2-2
January 2005
Rev. 3
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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