P4C1023-70CM datasheet, PDF - EEWORLD Datasheet

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P4C1023-70CM: DescriptionLOW POWER 128K x 8 SINGLE CHIP ENABLE CMOS STATIC RAM; Categorystorage storage; File Size335KB，11 Pages; ManufacturerPyramid Semiconductor Corporation; Websitehttp://www.pyramidsemiconductor.com/

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P4C1023-70CM Overview

LOW POWER 128K x 8 SINGLE CHIP ENABLE CMOS STATIC RAM

P4C1023-70CM Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Pyramid Semiconductor Corporation
Parts packaging code	DIP
package instruction	0.400 INCH, SIDE BRAZED, CERAMIC, DIP-32
Contacts	32
Reach Compliance Code	compli
ECCN code	3A001.A.2.C
Maximum access time	70 ns
JESD-30 code	R-CDIP-T32
JESD-609 code	e0
memory density	1048576 bi
Memory IC Type	STANDARD SRAM
memory width	8
Number of functions	1
Number of terminals	32
word count	131072 words
character code	128000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	128KX8
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	5.8928 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal surface	TIN LEAD
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.62 mm

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P4C1023/P4C1023L

LOW POWER 128K x 8

SINGLE CHIP ENABLE

CMOS STATIC RAM

FEATURES

Current

— Operating: 35mA

— CMOS Standby: 100µA

Access Times

—55/70 ns

Single 5 Volts ±10% Power Supply

Easy Memory Expansion Using

and

Inputs

Common Data I/O

Three-State Outputs

Fully TTL Compatible Inputs and Outputs

Advanced CMOS Technology

Automatic Power Down

Packages

—32-Pin 400 or 600 mil Ceramic DIP

—32-Pin Ceramic SOJ

DESCRIPTION

The P4C1023L is a 1 Megabit low power CMOS static

RAM organized as 128K x 8. The CMOS memory re-

quires no clocks or refreshing, and has equal access

and cycle times. Inputs are fully TTL-compatible. The

RAM operates from a single 5V±10% tolerance power

supply.

Access times of 55 ns and 70 ns are availale. CMOS is

utilized to reduce power consumption to a low level.

The P4C1023L device provides asynchronous opera-

tion with matching access and cycle times. Memory

locations are specified on address pins A

to A

. Read-

ing is accomplished by device selection (CE low) and

output enabling (OE) while write enable (WE) remains

HIGH. By presenting the address under these condi-

tions, the data in the addressed memory location is pre-

sented on the data input/output pins. The input/output

pins stay in the HIGH Z state when either

is HIGH or

is LOW.

The P4C1023L is packaged in a 32-pin 400 or 600 mil

ceramic DIP and in a 32-pin ceramic SOJ.

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATION

DIP (C10, C11), CERAMIC SOJ (CJ1)

TOP VIEW

Document #

SRAM126

REV OR

Revised October 2005

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