This product has been retired and is not recommended for designs. For new and current designs,
S29GL032M supersedes Am29PL320D and is the factory-recommended migration path. Please refer
to the S29GL032M datasheet for specifications and ordering information. Availability of this docu-
ment is retained for reference and historical purposes only.
June 2005
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that
originally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appro-
priate, and changes will be noted in a revision summary.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number
24075
Revision
C
Amendment
+3
Issue Date
June 13, 2005
THIS PAGE LEFT INTENTIONALLY BLANK.
Am29PL320D
32 Megabit (2 M x 16-Bit/1 M x 32-Bit)
CMOS 3.0 Volt-only High Performance Page Mode Flash Memory
This product has been retired and is not recommended for designs. For new and current designs, S29GL032M supersedes Am29PL320D and is the factory-recommended migration path.
Please refer to the S29GL032M datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only.
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
— Standby mode current: 2 µA
SOFTWARE FEATURES
■
32 Mbit Page Mode device
— Word (16-bit) or double word (32-bit) mode
selectable via WORD# input
— Page size of 8 words/4 double words: Fast page
read access from random locations within the
page
■
Single power supply operation
— Full voltage range: 2.7 to 3.6 volt read and write
operations for battery-powered applications
— Regulated voltage range: 3.0 to 3.6 volt read and
write operations and for compatibility with high
performance 3.3 volt microprocessors
■
Flexible sector architecture
— Sector sizes (x16 configuration): One 16 Kword,
two 8 Kword, one 96 Kword and fifteen 128
Kword sectors
— Supports full chip erase
■
SecSi
™
(Secured Silicon) Sector region
— Current version of device has 512 words (256
double words); future versions will have 128
words (64 double words)
■
Top or bottom boot block configuration
■
Manufactured on 0.23 µm process technology
■
20-year data retention at 125
°
C
■
Minimum 1 million erase cycles guarantee
per sector
PERFORMANCE CHARACTERISTICS
■
Software command-set compatible with JEDEC
standard
— Backward compatible with Am29F and Am29LV
families
■
CFI (Common Flash Interface) compliant
— Provides device-specific information to the
system, allowing host software to easily
reconfigure for different Flash devices
■
Unlock Bypass Program Command
— Reduces overall programming time when
issuing multiple program command sequences
■
Erase Suspend/Erase Resume
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
HARDWARE FEATURES
■
Sector Protection
— A hardware method of locking a sector to prevent
any program or erase operations within that
sector
— Sectors can be locked via programming
equipment
— Temporary Sector Unprotect command
sequence allows code changes in previously
locked sectors
■
ACC (Acceleration) input provides faster
programming times
■
WP# (Write Protect) input
— At V
IL
, protects the first or last 32 Kword sector,
regardless of sector protect/unprotect status
— At V
IH
, allows removal of sector protection
— An internal pull up to V
CC
is provided
■
Package Options
— 84-ball FBGA
■
High performance read access times
— Page access times as fast as 20 ns
— Random access times as fast as 60 ns
■
Power consumption (typical values)
— Initial page read current: 4 mA (1 MHz),
40 mA (10 MHz)
— Intra-page read current: 15 mA (10 MHz),
50 mA (33 MHz)
— Program/erase current: 25 mA
Publication#
24075
Rev:
C
Amendment/+3
Issue Date:
June 13, 2005
Refer to AMD’s Website (www.amd.com/flash) for the latest information.
GENERAL DESCRIPTION
The Am29PL320D is a 32 Mbit, 3.0 Volt-only page
mode Flash memory device organized as 2,097,152
words or 1,048,576 double words. The device is of-
fered in an 84-ball FBGA package. The word-wide
data (x16) appears on DQ15–DQ0; the double word-
wide (x32) data appears on DQ31–DQ0. The device is
available in both top and bottom boot versions. This
device can be programmed in-system or with in stan-
dard EPROM programmers. A 12.0 V V
PP
or 5.0 V
CC
are not required for write or erase operations.
The device offers fast page access times of 20, 25,
and 35 ns, with corresponding random access times of
60, 70, 90 ns, respectively, allowing high speed micro-
processors to operate without wait states. To eliminate
bus contention the device has separate chip enable
(CE#), write enable (WE#), and output enable (OE#)
controls.
before executing the erase operation. During erase,
the device automatically times the erase pulse widths
and verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by reading the DQ7
(Data# Polling) and DQ6 (toggle)
status bits.
After a
program or erase cycle has been completed, the device
is ready to read array data or accept another command.
The
sector erase architecture
allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The
hardware sector
protection
feature disables both program and erase
operations in any combination of the sectors of mem-
o r y. T h i s c a n b e a c h i ev e d i n - s y s t e m o r v i a
programming equipment.
The
Erase Suspend/Erase Resume
feature enables
the user to put erase on hold for any period of time to
read data from, or program data to, any sector that is
not selected for erasure. True background erase can
thus be achieved.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the
automatic sleep mode.
The system can also place the device into the
standby
mode.
Power consumption is greatly reduced in both
these modes.
The
SecSi
™
Sector
(Secured Silicon) is an extra sec-
tor capable of being permanently locked by AMD or
customers. The
SecSi Indicator Bit
(DQ7) is perma-
nently set to a 1 if the part is
factory locked,
and set
to a 0 if
customer lockable.
This way, customer lock-
able parts can never be used to replace a factory
locked par t.
Current version of device has 512
words (256 double words); future versions will
have only 128 words (64 double words). This
should be considered during system design.
Fac-
tory locked parts can store a secure, random 16 byte
ESN (Electronic Serial Number), customer code (pro-
grammed through AMD’s ExpressFlash service), or
both. Customer Lockable parts may be programmed
after being shipped from AMD.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunneling.
The data is programmed using hot electron injection.
Page Mode Features
The device is AC timing, input, output, and package
compatible with 16 Mbit x 16 page mode Mask
ROM.
The page size is 8 words or 4 double words.
After initial page access is accomplished, the page
mode operation provides fast read access speed of
random locations within that page.
Standard Flash Memory Features
The device requires only a
single 3.0 volt power sup-
ply
for both read and write functions. Inter nally
generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with
the
JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write cy-
cles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the
Embedded
Program
algor ithm—an inter nal algorithm that
automatically times the program pulse widths and
verifies proper cell margin. The
Unlock Bypass
mode
facilitates faster programming times by requiring only
two write cycles to program data instead of four.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the
Embedded Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already programmed)
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