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100353D

Description
D Flip-Flop
Categorylogic    logic   
File Size192KB,11 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
Download Datasheet Parametric Compare View All

100353D Overview

D Flip-Flop

100353D Parametric

Parameter NameAttribute value
package instruction,
Reach Compliance Codeunknown
Is SamacsysN
Logic integrated circuit typeD FLIP-FLOP
Certification statusNot Qualified
Base Number Matches1
100353 Low Power 8-Bit Register
August 1998
100353
Low Power 8-Bit Register
General Description
The 100353 contains eight D-type edge triggered, master/
slave flip-flops with individual inputs (D
n
), true outputs (Q
n
),
a clock input (CP), and a common clock enable pin (CEN).
Data enters the master when CP is LOW and transfers to the
slave when CP goes HIGH. When the CEN input goes HIGH
it overrides all other inputs, disables the clock, and the Q out-
puts maintain the last state.
The 100353 output drivers are designed to drive 50Ω termi-
nation to −2.0V. All inputs have 50 kΩ pull-down resistors.
Features
n
n
n
n
Low power operation
2000V ESD protection
Voltage compensated operating range = −4.2V to −5.7V
Available to MIL-STD-883
Logic Symbol
Pin Names
D
0
–D
7
CEN
CP
Q
0
–Q
7
NC
Data Inputs
Description
Clock Enable Input
Clock Input (Active Rising Edge)
Data Outputs
No Connect
DS100316-4
© 1998 National Semiconductor Corporation
DS100316
www.national.com

100353D Related Products

100353D Q16.0-JXS22-30-10/50-T3-LF 100353MW8
Description D Flip-Flop Parallel - Fundamental Quartz Crystal, D Flip-Flop
Reach Compliance Code unknown compliant unknown
Is Samacsys N - N
Logic integrated circuit type D FLIP-FLOP - D FLIP-FLOP
Certification status Not Qualified - Not Qualified
Base Number Matches 1 - 1

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