NB100LVEP224FAR2 datasheet, PDF

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NB100LVEP224FAR2: Description100LVE SERIES, LOW SKEW CLOCK DRIVER, 24 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP64; Categorysemiconductor logic; File Size97KB，10 Pages; ManufacturerON Semiconductor; Websitehttp://www.onsemi.cn

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NB100LVEP224FAR2 Overview

100LVE SERIES, LOW SKEW CLOCK DRIVER, 24 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP64

NB100LVEP224FAR2 Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	64
Minimum operating temperature	0.0 Cel
Maximum operating temperature	85 Cel
Rated supply voltage	2.5
Minimum supply/operating voltage	2.38 V
Maximum supply/operating voltage	3.8 V
Processing package description	LQFP-64
state	Active
Logic IC type	LOW SKEW CLOCK DRIVER
series	100LVE
Enter conditions	DIFFERENTIAL MUX
jesd_30_code	S-PQFP-G64
jesd_609_code	e0
moisture_sensitivity_level	NOT SPECIFIED
Number of inverted outputs	0.0
Real output number	24
Packaging Materials	PLASTIC/EPOXY
ckage_code	LFQFP
packaging shape	SQUARE
Package Size	FLATPACK, LOW PROFILE, FINE PITCH
eak_reflow_temperature__cel_	240
propagation delay TPD	0.7500 ns
qualification_status	COMMERCIAL
Maximum same-side bending	0.0400 ns
seated_height_max	1.6 mm
surface mount	YES
Craftsmanship	ECL
Temperature level	OTHER
terminal coating	TIN LEAD
Terminal form	GULL WING
Terminal spacing	0.5000 mm
Terminal location	QUAD
ime_peak_reflow_temperature_max__s_	30
length	10 mm
width	10 mm
dditional_feature	NECL MODE: VCC=0 WITH VEE = -2.375V TO -3.8V

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NB100LVEP224

2.5V/3.3V 1:24 Differential

ECL/PECL Clock Driver with

Clock Select and Output

Enable

The NB100LVEP224 is a low skew 1-to-24 differential clock

driver, designed with clock distribution in mind, accepting two clock

sources into an input multiplexer. The part is designed for use in low

voltage applications which require a large number of outputs to drive

precisely aligned low skew signals to their destination. The two clock

inputs are differential ECL/PECL and they are selected by the

CLK_SEL pin. To avoid generation of a runt clock pulse when the

device is enabled/disabled, the Output Enable (OE) is synchronous

ensuring the outputs will only be enabled/disabled when they are

already in LOW state (See Figure 4).

The NB100LVEP224 guarantees low output-to-output skew. The

optimal design, layout, and processing minimize skew within a device

and from lot to lot. In any differential output, the same bias and

termination scheme is required. Unused output pairs should be left

unterminated (open) to “reduce power and switching noise as much as

possible.” Any unused single line of a differential pair should be

terminated the same as the used line to maintain balanced loads on the

differential driver outputs. The wide VIHCMR specification allows

both pair of CLOCK inputs to accept LVDS levels.

The NB100LVEP224, as with most other ECL devices, can be

operated from a positive V

supply in LVPECL mode. This allows

the LVEP224 to be used for high performance clock distribution in

+3.3 V or +2.5 V systems. Single-ended CLK input operation is

limited to a V

≥

3.0 V in LVPECL mode, or V

≤

-3.0 V in NECL

mode. In a PECL environment, series or Thevenin line terminations

are typically used as they require no additional power supplies. For

more information on PECL terminations, designers should refer to

Application Note AND8020/D.

http://onsemi.com

MARKING

DIAGRAM*

NB100

LVEP224

AWLYYWW

64-LEAD LQFP

CASE 848G

THERMALLY ENHANCED

FA SUFFIX

= Assembly Location

= Wafer Lot

= Year

= Work Week

*For additional information, see Application Note

AND8002/D

ORDERING INFORMATION

Device

NB100LVEP224FA

Package

LQFP-64

Shipping

160 Units/Tray

•

NB100LVEP224FAR2 LQFP-64 1500/Tape & Reel

20 ps Typical Output-to-Output Skew

75 ps Typical Device-to- Device Skew

Maximum Frequency > 1 GHz

650 ps Typical Propagation Delay

LVPECL Mode Operating Range:

= 2.375 V to 3.8 V with V

= 0 V

•

NECL Mode Operating Range:

= 0 V with V

= -2.375 V to -3.8 V

•

Internal Input Pulldown Resistors

•

Q Output will Default Low with Inputs Open or at V

•

Thermally Enhanced 64-Lead LQFP

•

CLOCK Inputs are LVDS-Compatible; Requires External 100

LVDS Termination Resistor

Semiconductor Components Industries, LLC, 2003

June, 2003 - Rev. 4

Publication Order Number:

NB100LVEP224/D

NB100LVEP224FAR2 Related Products

	NB100LVEP224FAR2	NB100LVEP224	NB100LVEP224_06
Description	100LVE SERIES, LOW SKEW CLOCK DRIVER, 24 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP64	100LVE SERIES, LOW SKEW CLOCK DRIVER, 24 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP64	100LVE SERIES, LOW SKEW CLOCK DRIVER, 24 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP64
Number of functions	1	1	1
Number of terminals	64	64	64
Minimum operating temperature	0.0 Cel	0.0 Cel	0.0 Cel
Maximum operating temperature	85 Cel	85 Cel	85 Cel
Rated supply voltage	2.5	2.5 V	2.5 V
Minimum supply/operating voltage	2.38 V	2.38 V	2.38 V
Maximum supply/operating voltage	3.8 V	3.8 V	3.8 V
Processing package description	LQFP-64	LEAD FREE, LQFP-64	LEAD FREE, LQFP-64
state	Active	ACTIVE	ACTIVE
Logic IC type	LOW SKEW CLOCK DRIVER	LOW SKEW CLOCK DRIVER	LOW SKEW CLOCK DRIVER
series	100LVE	100LVE	100LVE
Enter conditions	DIFFERENTIAL MUX	DIFFERENTIAL MUX	DIFFERENTIAL MUX
Number of inverted outputs	0.0	0.0	0.0
Real output number	24	24	24
Packaging Materials	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
packaging shape	SQUARE	SQUARE	SQUARE
Package Size	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH
propagation delay TPD	0.7500 ns	0.7500 ns	0.7500 ns
Maximum same-side bending	0.0400 ns	0.0400 ns	0.0400 ns
surface mount	YES	Yes	Yes
Craftsmanship	ECL	ECL	ECL
Temperature level	OTHER	OTHER	OTHER
terminal coating	TIN LEAD	MATTE TIN	MATTE TIN
Terminal form	GULL WING	GULL WING	GULL WING
Terminal spacing	0.5000 mm	0.5000 mm	0.5000 mm
Terminal location	QUAD	QUAD	QUAD
Lead-free	-	Yes	Yes
EU RoHS regulations	-	Yes	Yes
China RoHS regulations	-	Yes	Yes

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