MT312
Satellite Channel Decoder
Design Manual
Supersedes DS5347 Issue 1.2 November 2001
DM5651
ISSUE 1.2
January 2002
Key Features
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•
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•
•
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Conforms to EBU specification for DVB-S and
DirecTV specification for DSS.
On-chip digital filtering supports 1 to 45MBaud
Symbol rates.
On-chip 6-bit 60 or 90MHz dual-ADC.
High speed scanning mode for blind symbol
rate/code rate acquisition.
Automatic IQ phase resolution.
No signal indicator.
Up to ±15MHz LNB frequency tracking.
Fully digital timing and phase recovery loops.
High level software interface for minimum
development time.
DiSEqC™ v2.2: receive/transmit for full control
of LNB and dish.
Ordering Information
MT312C/CG/GP1N
Applications
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DVB 1 to 45MBaud compliant satellite
receivers.
DSS 20MBaud compliant satellite receivers.
SCPC receivers. (Single Channel Per Carrier)
SMATV trans-modulators. (Single Master
Antenna TV)
LMDS (Local Multipoint Distribution Service)
Satellite PC applications.
The MT312 is a QPSK/BPSK 1 to 45MBaud
demodulator and channel decoder for digital satellite
television transmissions to the European Broadcast
Union ETS 300 421 specification (ref. 1). It receives
analogue I and Q signals from the tuner, digitises
and digitally demodulates this signal, and
implements the complete DVB/DSS FEC (Forward
Error Correction), and de-scrambling function. The
output is in the form of MPEG2 or DSS transport
stream data packets. An external MPEG clock input
is provided for synchronisation to MPEG decoders
and DVB Common Interface Modules. The MT312
also provides automatic gain control to the RF front-
end devices.
The MT312 has a serial 2-wire bus interface to the
control microprocessor. Minimal software is required
to control the MT312 because of the built in
automatic search and decode control functions.
AGC control
I
Q
Low pass
Filter
I I/P
Q I/P
Channel
Decoder
MT312
Transport
stream O/P
RF I/P
AGC
AMP
SL1914
Direct
Conversion
Tuner
SL1925
Tank
2-wire bus
control
Synthesiser
SP5769
2-wire bus control
Figure 1 - System Block Diagram - SNIM5
1
MT312
Design Manual
80
61
1
60
20
41
21
40
Figure 2 - System Block Diagram - SNIM5
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
FUNCTION
CVSS
CVDD
IIN[1]
ADDR[7]
ADDR[6]
ADDR[5]
ADDR[4]
ADDR[3]
CVDD
CVSS
ADDR[2]
ADDR[1]
VDD
MICLK
VSS
TESTCLK
CVDD
XTI
XTO
CVSS
PIN
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
FUNCTION
PLLVDD
PLLGND
PLL1
ADCFGND
ADCFVDD
VRT
IREF
ISINGP
NC
ADCDVDD
ADCDGND
VRM
QSINGP
QREF
VRB
ADCAGND
ADCAVDD
RREF
TEST1
TEST2
PIN
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
FUNCTION
CVSS
CVDD
AGC
CLK2/GPP0
DATA2/GPP1
DISEQC2/GPP2
DISEQC1 HV
DISEQC0 22kHz
RESET
CVDD
CVSS
STATUS
CLK1
DATA1
CVDD
VSS
IRQ
MOCLK
MDO[0]
CVSS
PIN
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
FUNCTION
MDO[1]
CVDD
MDO[2]
MDO[3]
MDO[4]
MDO[5]
CVDD
MDO[6]
MDO[7]
CVSS
MDOEN
MOVAL
VDD
VSS
BKERR
MOSTRT
IIN[5]
IIN[4]
IIN[3]
IIN[2]
Table 1 - MT312 pin-out
2
Design Manual
Quick start overview
The MT312 is a QPSK/BPSK 1 to 45MBaud
demodulator and channel decoder for digital satellite
television transmissions compliant to both DVB-S
and DSS standards and other systems, such as
LMDS, that use the same architecture.
A Command Driven Control (CDC) system is
provided making the MT312 very simple to program.
After the tuner has been programmed to the required
frequency, to acquire a DVB transmission, the
MT312 requires a minimum of five registers to be
written. Activity flow diagrams for initialisation and
basic channel change are included in section 2.
MT312
The MT312 provides a monitor of Bit Error Rate after
the QPSK module and also after the Viterbi module.
For receiver installation, a high speed scan or 'blind
search' mode is available. This allows all signals
from a given satellite to be evaluated for frequency,
symbol rate and convolutional coding scheme. The
phase of the IQ signals can be automatically
determined.
Full DiSEqC™ v2.2 is provided for both writing and
reading DiSEqC™ messages. Storage in registers
for up to eight data bytes sent and eight data bytes
received is provided.
MPEG/
DSS
Packets
I I/P
Dual ADC
Q I/P
De-rotator
Decimation
Filteriing
Timing recovery
Matched filter
Phase recovery
DVB
DSS
FEC
Analog
AG
Ccontrol
Clock Generation
Acquisition
Control
I?C
Interface
Bus I/O
Figure 3 - MT312 Functional Block Diagram
Additional Features
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2-wire bus microprocessor interface.
All digital clock and carrier recovery.
On-chip PLL clock generation using low cost 10
to 15MHz crystal.
3.3V operation.
80 pin MQFP package.
Low external component count.
Commercial temperature range 0 to 70°C.
De-Interleaver
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Compliant with DVB and DSS standards.
Reed Solomon
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(204, 188) for DVB and (146,130) for DSS.
Reed Solomon Bit-error-rate monitor to indicate
Viterbi performance.
De-Scrambler
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EBU specification De-scrambler for DVB mode.
Demodulator
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BPSK or QPSK programmable.
Optional fast acquisition mode for low symbol
rates.
Outputs
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MPEG transport parallel & serial output.
MPEG clock input for external synchronising of
MPEG data output.
Integrated MPEG2 TEI bit processing for DVB
only.
Viterbi
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Programmable decoder rates 1/2, 2/3, 3/4, 5/6,
6/7, 7/8.
Automatic spectrum resolution of IQ phase.
Constraint length k=7.
Trace back depth 128.
Extensive SNR and BER monitors.
Application Support
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Channel decoder system evaluation board.
Windows based evaluation software.
ANSI C generic software.
3
MT312
Contents
1
1.1
1.2
1.3
1.4
1.4.1.1
1.4.1.2
1.4.2
1.4.3
1.4.3.1
1.4.3.2
1.4.4
1.4.5
1.4.6
1.5
1.5.2
1.6
1.7
1.7.1
1.7.2
Contents
Functional Overview ............................................................................................. 10
Introduction ........................................................................................................................................ 10
Analogue-to-Digital Converter ............................................................................................................ 10
QPSK Demodulator ............................................................................................................................ 10
Forward Error Correction .................................................................................................................. 11
Viterbi Error Count Measurement ................................................................................................ 11
Viterbi Error Count Coarse Indication .......................................................................................... 12
The Frame Alignment Block ........................................................................................................ 12
The De-interleaver Block ............................................................................................................. 13
DVB ............................................................................................................................................. 13
DSS ............................................................................................................................................. 13
The Reed Solomon Decoder Block ............................................................................................. 14
The Energy Dispersal (De-Scrambler) Block, DVB only .............................................................. 14
Output Stage ............................................................................................................................... 15
Control ................................................................................................................................................ 15
Symbol Rate and Code Rate Search Mode ................................................................................ 16
Direct Conversion Application ............................................................................................................ 16
DiSEqC™ Transmit and Receive Messages ..................................................................................... 17
DiSEqC™ Transmitting Messages .............................................................................................. 17
DiSEqC™ Receiving Messages .................................................................................................. 17
2
2.1
MT312 Software Control ....................................................................................... 18
MT312 Register Map Overview .......................................................................................................... 18
3
3.1
3.2
3.3
3.4
3.5
3.5.1
3.5.2
3.5.3
3.6
3.6.1
MT312 Initialisation ............................................................................................... 19
The Configuration Register (127) ....................................................................................................... 19
Power Supplies ................................................................................................................................... 19
Initialisation Sequence ....................................................................................................................... 20
Spectral Inversion .............................................................................................................................. 21
MT312 Initialisation Read/Write Registers ......................................................................................... 21
Reset. Register 21 (R/W) ........................................................................................................... 21
MT312 Configuration. Register 127 (R/W) ................................................................................. 22
System Clock Frequency. Register 34 (R/W) ............................................................................. 23
MT312 Initialisation Read Register .................................................................................................... 23
Identification. Register 126 (R) ................................................................................................... 23
4
4.1
4.2
4.3
4.4
4.4.1
4.4.2
4.4.3
4.5
4.5.1
4.5.2
Tuner Control ......................................................................................................... 24
Simple Channel Change Sequence ................................................................................................... 24
Channel Change Sequence with a new Symbol Rate ....................................................................... 24
Channel Change Sequence with Search Mode ................................................................................. 24
Tuner Control Read/Write Registers .................................................................................................. 25
General Purpose Port Control. Register 20 (R/W) ..................................................................... 25
FR LIM: Frequency Limit. Register 37 (R/W) ............................................................................. 26
FR OFF: Frequency Offset. Register 38 (R/W) .......................................................................... 27
Tuner Control Read Registers ........................................................................................................... 27
Measured LNB Frequency Error. Registers 7 - 8 (R) ........................................................................ 27
Frequency Error 1 and 2. Registers 111 - 115 (R) ............................................................................ 28
4
Contents
5
5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.3
5.3.1
5.3.2
5.3.3
MT312
DiSEqC Control ......................................................................................................29
Screen Printouts of DiSEqC™ Waveforms ........................................................................................ 29
DiSEqC Control Read/Write Registers ............................................................................................... 30
DiSEqC™ Mode Control. Register 22 (R/W) .............................................................................. 30
DiSEqC(tm) Ratio. Register 35 (R/W) ........................................................................................ 30
DiSEqC™ Instruction (R/W). Register 36 (R/W) ........................................................................ 31
DiSEqC™ 2 Control 1. Registers 121 (R/W) .............................................................................. 31
DiSEqCTM 2 Control 2. Registers 122 (R/W) ............................................................................ 32
DiSEqC Control Read Registers ........................................................................................................ 33
DiSEqC™M 2 Interrupt Indicators. Register 118 (R) .................................................................. 33
DiSEqC™M 2 Status Indicators. Register 119 (R) ..................................................................... 34
DiSEqC™ 2 FIFO. Register 120 (R) ........................................................................................... 34
6
6.1
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.2
6.2.1
6.2.2
6.2.3
6.2.4
QPSK demodulator ................................................................................................36
QPSK Demodulator Read/Write Registers ........................................................................................ 36
Symbol Rate. Registers 23 - 24 (R/W) ....................................................................................... 36
Viterbi mode. Register 25 (R/W) ................................................................................................. 38
QPSK Control. Register 26 (R/W) .............................................................................................. 39
Go Command. Register 27 (R/W) .............................................................................................. 40
QPSK Interrupt Output Enable. Registers 28 - 30 (R/W) ........................................................... 40
QPSK STATUS Output Enable. Register 32 (R/W) .................................................................... 41
QPSK Demodulator Read Registers .................................................................................................. 42
QPSK Interrupt. Registers 0 - 2 (R) ............................................................................................ 42
QPSK Status. Registers 4 - 5 (R) ............................................................................................... 44
Symbol Rate Output. Registers 116 - 117 (R) ............................................................................ 44
Monitor Registers. Registers 123 - 124 (R) ................................................................................ 45
7
7.1
7.1.1
7.1.2
7.1.3
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
Forward Error Correction ......................................................................................46
Forward Error Correction Read/Write Registers ................................................................................ 47
FEC Interrupt Enable. Register 31 (R/W) ................................................................................... 47
FEC STATUS Output Enable. Register 33 (R/W) ...................................................................... 47
FEC Set Up. Register 97 (R/W) .................................................................................................. 48
Forward Error Correction Read Registers .......................................................................................... 48
FEC Interrupt. Register 3 (R) ...................................................................................................... 48
FEC Status. Register 6 (R) ......................................................................................................... 49
Measured Signal to Noise Ratio. Registers 9 - 10 (R) ................................................................ 49
Viterbi Error Count at Viterbi Input. Registers 11 - 13 (R) .......................................................... 50
Reed Solomon Bit Errors Corrected. Registers 14 - 16 (R) ........................................................ 50
Reed Solomon Uncorrected block Errors. Registers 17 - 18 (R) ................................................ 51
8
8.1
8.1.1
8.1.2
8.2
8.2.1
8.2.2
Automatic Gain Control ........................................................................................52
Automatic Gain Control Read/Write Registers ................................................................................... 52
AGC Control. Register 39 (R/W) ................................................................................................ 52
AGC REF Reference Value. Register 41 (R/W) ......................................................................... 52
Automatic Gain Control Read Registers ............................................................................................ 53
Measured Signal Level at MT312 Input. Register 19 (R) ........................................................... 53
Measured AGC Feed Back Value. Registers 108 - 110 (R) ....................................................... 53
9
9.1
9.2
9.3
9.4
9.5
9.5.1
9.5.2
MPEG Packet Data Ouput .....................................................................................54
MPEG Clock Modes ........................................................................................................................... 54
Data Output Header Format - DVB only ............................................................................................ 55
MPEG/DSS Data Output Signals ....................................................................................................... 56
Data output timing .............................................................................................................................. 58
MPEG Packet Data Output Read/Write Registers ............................................................................. 59
Output Data Control. Register 96 (R/W) ..................................................................................... 59
Monitor Control. Register 103 (R/W) .......................................................................................... 59
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