M24C16, M24C08
M24C04, M24C02, M24C01
16/8/4/2/1 Kbit Serial I²C Bus EEPROM
s
Two Wire I
2
C Serial Interface
Supports 400 kHz Protocol
Single Supply Voltage:
– 4.5V to 5.5V for M24Cxx
– 2.5V to 5.5V for M24Cxx-W
– 1.8V to 3.6V for M24Cxx-R
s
8
1
PSDIP8 (BN)
0.25 mm frame
s
s
s
s
s
s
s
s
Hardware Write Control
BYTE and PAGE WRITE (up to 16 Bytes)
RANDOM and SEQUENTIAL READ Modes
Self-Timed Programming Cycle
Automatic Address Incrementing
Enhanced ESD/Latch-Up Behaviour
1 Million Erase/Write Cycles (minimum)
40 Year Data Retention (minimum)
8
1
SO8 (MN)
150 mil width
8
1
TSSOP8 (DW)
169 mil width
DESCRIPTION
These electrically erasable programmable memo-
ry (EEPROM) devices are fabricated with STMi-
croelectronics’
High
Endurance,
Single
Polysilicon, CMOS technology. This guarantees
an endurance typically well above one million
Erase/Write cycles, with a data retention of
40 years. The memories are organised as 2048/
1024 x 8 bit (M24C16, M24C08) and 512/256/128
x 8 bit (M24C04, M24C02, M24C01), and operate
with a power supply down to 2.5 V (for the -W ver-
Figure 1. Logic Diagram
VCC
Table 1. Signal Names
E0, E1, E2
SDA
Chip Enable Inputs
Serial Data/Address Input/
Output
Serial Clock
Write Control
Supply Voltage
Ground
3
E0-E2
SCL
WC
M24Cxx
SDA
SCL
WC
V
CC
V
SS
VSS
AI02033
March 1999
1/17
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 2A. DIP Connections
M24Cxx
M24Cxx - W
M24Cxx - R
E0
E1
E2
VSS
Note: 1.
2.
3.
4.
Figure 2C. Standard-TSSOP Connections
M24C01/02/04
M24C01/02/04 - W
M24C01/02/04 - R
M24C08/16 - R
VCC
WC
SCL
SDA
E0
E1
E2
VSS
1
2
3
4
8
7
6
5
AI02036B
1
2
3
4
8
7
6
5
AI02034B
VCC
WC
SCL
SDA
xx = 01, 02, 04, 08 or 16
Pin 1 is Not Connected for 4 Kbit devices
Pins 1 and 2 are Not Connected for 8 Kbit devices
Pins 1, 2 and 3 are Not Connected for 16 Kbit devices
Note: 1. Pin 1 is Not Connected for 4 Kbit devices
2. Pins 1 and 2 are Not Connected for 8 Kbit devices
3. Pins 1, 2 and 3 are Not Connected for 16 Kbit devices
Figure 2B. SO Connections
M24Cxx
M24Cxx - W
M24Cxx - R
E0
E1
E2
VSS
Note: 1.
2.
3.
4.
Figure 2D. Turned-TSSOP Connections
M24C08/16 - T
M24C08/16 - TW
VCC
WC
SCL
SDA
WC
VCC
NC
NC
1
2
3
4
8
7
6
5
AI02216B
1
2
3
4
8
7
6
5
AI02035B
SCL
SDA
VSS
E2/NC
xx = 01, 02, 04, 08 or 16
Pin 1 is Not Connected for 4 Kbit devices
Pins 1 and 2 are Not Connected for 8 Kbit devices
Pins 1, 2 and 3 are Not Connected for 16 Kbit devices
Note: 1. NC = Not Connected
2. Pin 5 is Not Connected for 16 Kbit devices
Table 2. Absolute Maximum Ratings
1
Symbol
T
A
T
STG
T
LEAD
V
IO
V
CC
V
ESD
Electrostatic Discharge Voltage (Machine model)
3
500
V
Note: 1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.
2. MIL-STD-883C, 3015.7 (100 pF, 1500
Ω)
3. EIAJ IC-121 (Condition C) (200 pF, 0
Ω)
Parameter
Ambient Operating Temperature
Storage Temperature
Lead Temperature during Soldering
Input or Output range
Supply Voltage
Electrostatic Discharge Voltage (Human Body model)
2
PSDIP8: 10 sec
SO8: 40 sec
TSSOP8: t.b.c.
Value
-40 to 125
-65 to 150
260
215
t.b.c.
-0.6 to 6.5
-0.3 to 6.5
4000
Unit
°C
°C
°C
V
V
V
2/17
M24C16, M24C08, M24C04, M24C02, M24C01
sion of each device), and down to 1.8 V (for the -R
version of each device).
The M24C16, M24C08, M24C04, M24C02,
M24C01 are available in Plastic Dual-in-Line,
Plastic Small Outline and Thin Shrink Small Out-
line packages.
These memory devices are compatible with the
I
2
C memory standard. This is a two wire serial in-
terface that uses a bi-directional data bus and se-
rial clock. The memory carries a built-in 4-bit
unique Device Type Identifier code (1010) in ac-
cordance with the I
2
C bus definition.
The memory behaves as a slave device in the I
2
C
protocol, with all memory operations synchronized
by the serial clock. Read and Write operations are
initiated by a START condition, generated by the
bus master. The START condition is followed by a
Device Select Code and RW bit (as described in
Table 3), terminated by an acknowledge bit.
When writing data to the memory, the memory in-
serts an acknowledge bit during the 9
th
bit time,
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a STOP condition after an Ack for WRITE, and af-
ter a NoAck for READ.
Power On Reset: V
CC
Lock-Out Write Protect
In order to prevent data corruption and inadvertent
write operations during power up, a Power On Re-
set (POR) circuit is included. The internal reset is
held active until the V
CC
voltage has reached the
POR threshold value, and all operations are dis-
abled – the device will not respond to any com-
mand. In the same way, when V
CC
drops from the
operating voltage, below the POR threshold value,
all operations are disabled and the device will not
respond to any command. A stable and valid V
CC
must be applied before applying any logic signal.
SIGNAL DESCRIPTION
Serial Clock (SCL)
The SCL input pin is used to strobe all data in and
out of the memory. In applications where this line
is used by slaves to synchronize the bus to a slow-
er clock, the master must have an open drain out-
put, and a pull-up resistor must be connected from
the SCL line to V
CC
. (Figure 3 indicates how the
value of the pull-up resistor can be calculated). In
most applications, though, this method of synchro-
nization is not employed, and so the pull-up resis-
tor is not necessary, provided that the master has
a push-pull (rather than open drain) output.
Serial Data (SDA)
The SDA pin is bi-directional, and is used to trans-
fer data in or out of the memory. It is an open drain
output that may be wire-OR’ed with other open
drain or open collector signals on the bus. A pull
up resistor must be connected from the SDA bus
to V
CC
. (Figure 3 indicates how the value of the
pull-up resistor can be calculated).
Chip Enable (E2, E1, E0)
These chip enable inputs are used to set the value
that is to be looked for on the three least significant
bits (b3, b2, b1) of the 7-bit device select code (but
see the description of memory addressing, on
page 5, for more details). These inputs may be
driven dynamically or tied to V
CC
or V
SS
to estab-
lish the device select code (but note that the V
IL
and V
IH
levels for the inputs are CMOS compati-
ble, not TTL compatible).
Figure 3. Maximum R
L
Value versus Bus Capacitance (C
BUS
) for an I
2
C Bus
VCC
20
Maximum RP value (kΩ)
16
RL
12
8
4
0
10
100
CBUS (pF)
AI01665
RL
SDA
MASTER
fc = 100kHz
fc = 400kHz
SCL
CBUS
CBUS
1000
3/17
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 4. I
2
C Bus Protocol
SCL
SDA
START
CONDITION
SDA
INPUT
SDA
CHANGE
STOP
CONDITION
SCL
1
2
3
7
8
9
SDA
MSB
ACK
START
CONDITION
SCL
1
2
3
7
8
9
SDA
MSB
ACK
STOP
CONDITION
AI00792
Write Control (WC)
The hardware Write Control pin (WC) is useful for
protecting the entire contents of the memory from
inadvertent erase/write. The Write Control signal is
used to enable (WC=V
IL
) or disable (WC=V
IH
)
write instructions to the entire memory area. When
unconnected, the WC input is internally read as
V
IL
, and write operations are allowed.
When WC=1, Device Select and Address bytes
are acknowledged, Data bytes are not acknowl-
edged.
Please see the Application Note
AN404
for a more
detailed description of the Write Control feature.
DEVICE OPERATION
The memory device supports the I
2
C protocol.
This is summarized in Figure 4, and is compared
with other serial bus protocols in Application Note
AN1001.
Any device that sends data on to the bus
is defined to be a transmitter, and any device that
reads the data to be a receiver. The device that
controls the data transfer is known as the master,
and the other as the slave. A data transfer can only
be initiated by the master, which will also provide
the serial clock for synchronization. The memory
device is always a slave device in all communica-
tion.
Start Condition
START is identified by a high to low transition of
the SDA line while the clock, SCL, is stable in the
high state. A START condition must precede any
data transfer command. The memory device con-
tinuously monitors (except during a programming
cycle) the SDA and SCL lines for a START condi-
tion, and will not respond unless one is given.
Stop Condition
STOP is identified by a low to high transition of the
SDA line while the clock SCL is stable in the high
state. A STOP condition terminates communica-
4/17
M24C16, M24C08, M24C04, M24C02, M24C01
Table 3. Device Select Code
1
Device Type Identifier
b7
M24C01 Select Code
M24C02 Select Code
M24C04 Select Code
M24C08 Select Code
M24C16 Select Code
1
1
1
1
1
b6
0
0
0
0
0
b5
1
1
1
1
1
b4
0
0
0
0
0
b3
E2
E2
E2
E2
A10
Chip Enable
b2
E1
E1
E1
A9
A9
b1
E0
E0
A8
A8
A8
RW
b0
RW
RW
RW
RW
RW
Note: 1. The most significant bit, b7, is sent first.
2. E0, E1 and E2 are compared against the respective external pins on the memory device.
3. A10, A9 and A8 represent high significant bits of the address.
tion between the memory device and the bus mas-
ter. A STOP condition at the end of a Read
command, after (and only after) a NoAck, forces
the memory device into its standby state. A STOP
condition at the end of a Write command triggers
the internal EEPROM write cycle.
Acknowledge Bit (ACK)
An acknowledge signal is used to indicate a suc-
cessful byte transfer. The bus transmitter, whether
it be master or slave, releases the SDA bus after
sending eight bits of data. During the 9
th
clock
pulse period, the receiver pulls the SDA bus low to
acknowledge the receipt of the eight data bits.
Data Input
During data input, the memory device samples the
SDA bus signal on the rising edge of the clock,
SCL. For correct device operation, the SDA signal
must be stable during the clock low-to-high transi-
tion, and the data must change
only
when the SCL
line is low.
Memory Addressing
To start communication between the bus master
and the slave memory, the master must initiate a
START condition. Following this, the master sends
the 8-bit byte, shown in Table 3, on the SDA bus
line (most significant bit first). This consists of the
Table 4. Operating Modes
Mode
Current Address Read
Random Address Read
‘1’
Sequential Read
Byte Write
Page Write
Note: 1. X =
V
IH
or V
IL
.
7-bit Device Select Code, and the 1-bit Read/Write
Designator (RW). The Device Select Code is fur-
ther subdivided into: a 4-bit Device Type Identifier,
and a 3-bit Chip Enable “Address” (E2, E1, E0).
To address the memory array, the 4-bit Device
Type Identifier is 1010b.
If all three chip enable inputs are connected, up to
eight memory devices can be connected on a sin-
gle I
2
C bus. Each one is given a unique 3-bit code
on its Chip Enable inputs. When the Device Se-
lect Code is received on the SDA bus, the memory
only responds if the Chip Select Code is the same
as the pattern applied to its Chip Enable pins.
Those devices with larger memory capacities (the
M24C16, M24C08) need more address bits. E0 is
not available for use on devices that need to use
address line A8; E1 is not available for devices
that need to use address line A9, and E2 is not
available for devices that need to use address line
A10 (see Figure 2A to Figure 2D for details). Using
the E0, E1 and E2 inputs pins, up to eight M24C02
(or M24C01), four M24C04, two M24C08 or one
M24C16 device can be connected to one I
2
C bus.
In each case, and in the hybrid cases, this gives a
total memory capacity of 16 Kbits, 2 KBytes (ex-
cept where M24C01 devices are used).
RW bit
‘1’
‘0’
WC
1
X
X
Bytes
1
1
Initial Sequence
START, Device Select, RW = ‘1’
START, Device Select, RW = ‘0’, Address
reSTART, Device Select, RW = ‘1’
X
X
V
IL
V
IL
≥
1
1
≤
16
‘1’
‘0’
‘0’
Similar to Current or Random Address Read
START, Device Select, RW = ‘0’
START, Device Select, RW = ‘0’
5/17
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