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EDI88512CA35NB

Description
Standard SRAM, 512KX8, 35ns, CMOS, CDSO32, CERAMIC, SOJ-32
Categorystorage    storage   
File Size1MB,10 Pages
ManufacturerMercury Systems Inc
Download Datasheet Parametric View All

EDI88512CA35NB Overview

Standard SRAM, 512KX8, 35ns, CMOS, CDSO32, CERAMIC, SOJ-32

EDI88512CA35NB Parametric

Parameter NameAttribute value
package instructionSOJ,
Reach Compliance Codeunknown
ECCN code3A001.A.2.C
Is SamacsysN
Maximum access time35 ns
JESD-30 codeR-CDSO-J32
length21.082 mm
memory density4194304 bit
Memory IC TypeSTANDARD SRAM
memory width8
Number of functions1
Number of terminals32
word count524288 words
character code512000
Operating modeASYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize512KX8
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeSOJ
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Parallel/SerialPARALLEL
Maximum seat height3.937 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationDUAL
width11.0998 mm
Base Number Matches1
EDI88512CA
512Kx8 Monolithic SRAM, SMD 5962-95600
FEATURES

Access Times of 15, 17, 20, 25, 35, 45, 55ns

Data Retention Function (LPA version)

TTL Compatible Inputs and Outputs

Fully Static, No Clocks

Organized as 512Kx8

Commercial, Industrial and Military Temperature Ranges

32 lead JEDEC Approved Evolutionary Pinout
• Ceramic Sidebrazed 600 mil DIP (Package 9)
• Ceramic Sidebrazed 400 mil DIP (Package 326)
• Ceramic 32 pin Flatpack (Package 344)
• Ceramic Thin Flatpack (Package 321)
• Ceramic SOJ (Package 140)

36 lead JEDEC Approved Revolutionary Pinout
• Ceramic Flatpack (Package 316)
• Ceramic SOJ (Package 327)
• Ceramic LCC (Package 502)

Single +5V (±10%) Supply Operation
*This product is subject to change without notice.
The EDI88512CA is a 4 megabit Monolithic CMOS Static RAM.
The 32 pin DIP pinout adheres to the JEDEC evolutionary standard
for the four megabit device. All 32 pin packages are pin for pin
upgrades for the single chip enable 128K x 8, the EDI88128CS.
Pins 1 and 30 become the higher order addresses.
The 36 pin revolutionary pinout also adheres to the JEDEC
standard for the four megabit device. The center pin power and
ground pins help to reduce noise in high performance systems.
The 36 pin pinout also allows the user an upgrade path to the
future 2Mx8.
A Low Power version with Data Retention (EDI88512LPA) is
also available for battery backed applications. Military product is
available compliant to Appendix A of MIL-PRF-38535.
FIGURE 1 – PIN CONFIGURATION
I/O
0-7
A0
-18
WE#
CS#
OE#
PIN DESCRIPTION
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power (+5V ±10%)
Ground
Not Connected
36 PIN
TOP VIEW
A0
A1
A2
A3
A4
CS#
I/O0
I/O1
Vcc
Vss
I/O2
I/O3
WE#
A5
A6
A7
A8
A9
1
2
3
4
5
6
7
8
36 pin
9
10
Revolutionary
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
A18
A17
A16
A15
OE#
I/O7
I/O6
Vss
Vcc
I/O5
I/O4
A14
A13
A12
A11
A10
NC
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 PIN
TOP VIEW
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A15
A17
WE#
A13
A8
A9
A11
OE#
A10
CS#
I/O7
I/O6
I/O5
I/O4
I/O3
V
CC
V
SS
NC
BLOCK DIAGRAM
Memory Array
32 pin
Evolutionary
A
0-18
Address
Buffer
Address
Decoder
I/O
Circuits
I/O
0-7
WE#
CS#
OE#
Microsemi Corporation reserves the right to change products or specifications without notice.
May 2014
Rev. 15
© 2014 Microsemi Corporation. All rights reserved.
1
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
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