MC10117FN datasheet, PDF - EEWORLD Datasheet

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MC10117FN: DescriptionDual 2-Wide 2-3-Input OR-AND/OR-AND Gate; Categorylogic logic; File Size108KB，8 Pages; ManufacturerON Semiconductor; Websitehttp://www.onsemi.cn

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MC10117FN Overview

Dual 2-Wide 2-3-Input OR-AND/OR-AND Gate

MC10117FN Parametric

Parameter Name	Attribute value
Parts packaging code	QLCC
package instruction	QCCJ, LDCC20,.4SQ
Contacts	20
Reach Compliance Code	compli
Is Samacsys	N
series	10K
JESD-30 code	S-PQCC-J20
length	8.965 mm
Logic integrated circuit type	OR-AND/OR-AND-INVERT GATE
Number of functions	2
Number of entries	5
Number of terminals	20
Maximum operating temperature	85 °C
Minimum operating temperature	-30 °C
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC20,.4SQ
Package shape	SQUARE
Package form	CHIP CARRIER
power supply	-5.2 V
Maximum supply current (ICC)	29 mA
Prop。Delay @ Nom-Su	3.8 ns
propagation delay (tpd)	3.4 ns
Certification status	Not Qualified
Schmitt trigger	NO
Maximum seat height	4.57 mm
surface mount	YES
technology	ECL
Temperature level	OTHER
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
width	8.965 mm
Base Number Matches	1

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MC10117

Dual 2-Wide 2-3-Input

OR-AND/OR-AND Gate

T h e M C 1 0 11 7 i s a d u a l 2 – w i d e 2 – 3 – i n p u t

OR–AND/OR–AND–Invert gate. This general purpose logic element

is designed for use in data control, such as digital multiplexing or data

distribution. Pin 9 is common to both gates.

•

= 100 mW typ/pkg (No Load)

•

= 2.3 ns typ

•

, t

= 2.2 ns typ (20%–80%)

LOGIC DIAGRAM

CC1

= PIN 1

CC2

= PIN 16

= PIN 8

PLCC–20

FN SUFFIX

CASE 775

PDIP–16

P SUFFIX

CASE 648

10117

AWLYYWW

http://onsemi.com

MARKING

DIAGRAMS

CDIP–16

L SUFFIX

CASE 620

MC10117P

AWLYYWW

MC10117L

AWLYYWW

DIP

PIN ASSIGNMENT

CC1

OUT

CC2

OUT

, B2

MC10117P

= Assembly Location

= Wafer Lot

= Year

= Work Week

ORDERING INFORMATION

Device

MC10117L

Package

CDIP–16

PDIP–16

PLCC–20

Shipping

25 Units / Rail

46 Units / Rail

MC10117FN

Pin assignment is for Dual–in–Line Package.

For PLCC pin assignment, see the Pin Conversion Tables on page 18

of the ON Semiconductor MECL Data Book (DL122/D).

Semiconductor Components Industries, LLC, 2002

January, 2002 – Rev. 7

Publication Order Number:

MC10117/D

MC10117FN Related Products

	MC10117FN	MC10117L	MC10117_02	MC10117	MC10117P
Description	Dual 2-Wide 2-3-Input OR-AND/OR-AND Gate	Dual 2-Wide 2-3-Input OR-AND/OR-AND Gate	Dual 2-Wide 2-3-Input OR-AND/OR-AND Gate	Dual 2-Wide 2-3-Input OR-AND/OR-AND Gate	Dual 2-Wide 2-3-Input OR-AND/OR-AND Gate
Parts packaging code	QLCC	DIP	-	-	DIP
package instruction	QCCJ, LDCC20,.4SQ	CERAMIC, DIP-16	-	-	PLASTIC, DIP-16
Contacts	20	16	-	-	16
Reach Compliance Code	compli	_compli	-	-	_compli
series	10K	10K	-	-	10K
JESD-30 code	S-PQCC-J20	R-GDIP-T16	-	-	R-PDIP-T16
length	8.965 mm	19.49 mm	-	-	19.175 mm
Logic integrated circuit type	OR-AND/OR-AND-INVERT GATE	OR-AND/OR-AND-INVERT GATE	-	-	OR-AND/OR-AND-INVERT GATE
Number of functions	2	2	-	-	2
Number of entries	5	5	-	-	5
Number of terminals	20	16	-	-	16
Maximum operating temperature	85 °C	85 °C	-	-	85 °C
Minimum operating temperature	-30 °C	-30 °C	-	-	-30 °C
Package body material	PLASTIC/EPOXY	CERAMIC, GLASS-SEALED	-	-	PLASTIC/EPOXY
encapsulated code	QCCJ	DIP	-	-	DIP
Encapsulate equivalent code	LDCC20,.4SQ	DIP16,.3	-	-	DIP16,.3
Package shape	SQUARE	RECTANGULAR	-	-	RECTANGULAR
Package form	CHIP CARRIER	IN-LINE	-	-	IN-LINE
power supply	-5.2 V	-5.2 V	-	-	-5.2 V
Maximum supply current (ICC)	29 mA	29 mA	-	-	29 mA
Prop。Delay @ Nom-Su	3.8 ns	3.8 ns	-	-	3.8 ns
propagation delay (tpd)	3.4 ns	3.4 ns	-	-	3.4 ns
Certification status	Not Qualified	Not Qualified	-	-	Not Qualified
Schmitt trigger	NO	NO	-	-	NO
Maximum seat height	4.57 mm	5.08 mm	-	-	4.44 mm
surface mount	YES	NO	-	-	NO
technology	ECL	ECL	-	-	ECL
Temperature level	OTHER	OTHER	-	-	OTHER
Terminal form	J BEND	THROUGH-HOLE	-	-	THROUGH-HOLE
Terminal pitch	1.27 mm	2.54 mm	-	-	2.54 mm
Terminal location	QUAD	DUAL	-	-	DUAL
width	8.965 mm	7.62 mm	-	-	7.62 mm

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