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MC10117

Description
Dual 2-Wide 2-3-Input OR-AND/OR-AND Gate
File Size108KB,8 Pages
ManufacturerON Semiconductor
Websitehttp://www.onsemi.cn
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MC10117 Overview

Dual 2-Wide 2-3-Input OR-AND/OR-AND Gate

MC10117
Dual 2-Wide 2-3-Input
OR-AND/OR-AND Gate
T h e M C 1 0 11 7 i s a d u a l 2 – w i d e 2 – 3 – i n p u t
OR–AND/OR–AND–Invert gate. This general purpose logic element
is designed for use in data control, such as digital multiplexing or data
distribution. Pin 9 is common to both gates.
P
D
= 100 mW typ/pkg (No Load)
t
pd
= 2.3 ns typ
t
r
, t
f
= 2.2 ns typ (20%–80%)
LOGIC DIAGRAM
4
5
6
7
9
10
11
12
13
14
15
V
CC1
= PIN 1
V
CC2
= PIN 16
V
EE
= PIN 8
PLCC–20
FN SUFFIX
CASE 775
3
2
PDIP–16
P SUFFIX
CASE 648
1
1
10117
AWLYYWW
http://onsemi.com
MARKING
DIAGRAMS
16
CDIP–16
L SUFFIX
CASE 620
1
16
MC10117P
AWLYYWW
MC10117L
AWLYYWW
DIP
PIN ASSIGNMENT
V
CC1
A
OUT
A
OUT
A1
IN
A1
IN
A2
IN
A2
IN
V
EE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC2
B
OUT
B
OUT
B1
IN
B1
IN
B2
IN
B2
IN
A2
IN
, B2
IN
MC10117P
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Device
MC10117L
Package
CDIP–16
PDIP–16
PLCC–20
Shipping
25 Units / Rail
25 Units / Rail
46 Units / Rail
MC10117FN
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
©
Semiconductor Components Industries, LLC, 2002
1
January, 2002 – Rev. 7
Publication Order Number:
MC10117/D

MC10117 Related Products

MC10117 MC10117L MC10117_02 MC10117P MC10117FN
Description Dual 2-Wide 2-3-Input OR-AND/OR-AND Gate Dual 2-Wide 2-3-Input OR-AND/OR-AND Gate Dual 2-Wide 2-3-Input OR-AND/OR-AND Gate Dual 2-Wide 2-3-Input OR-AND/OR-AND Gate Dual 2-Wide 2-3-Input OR-AND/OR-AND Gate
Parts packaging code - DIP - DIP QLCC
package instruction - CERAMIC, DIP-16 - PLASTIC, DIP-16 QCCJ, LDCC20,.4SQ
Contacts - 16 - 16 20
Reach Compliance Code - _compli - _compli compli
series - 10K - 10K 10K
JESD-30 code - R-GDIP-T16 - R-PDIP-T16 S-PQCC-J20
length - 19.49 mm - 19.175 mm 8.965 mm
Logic integrated circuit type - OR-AND/OR-AND-INVERT GATE - OR-AND/OR-AND-INVERT GATE OR-AND/OR-AND-INVERT GATE
Number of functions - 2 - 2 2
Number of entries - 5 - 5 5
Number of terminals - 16 - 16 20
Maximum operating temperature - 85 °C - 85 °C 85 °C
Minimum operating temperature - -30 °C - -30 °C -30 °C
Package body material - CERAMIC, GLASS-SEALED - PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code - DIP - DIP QCCJ
Encapsulate equivalent code - DIP16,.3 - DIP16,.3 LDCC20,.4SQ
Package shape - RECTANGULAR - RECTANGULAR SQUARE
Package form - IN-LINE - IN-LINE CHIP CARRIER
power supply - -5.2 V - -5.2 V -5.2 V
Maximum supply current (ICC) - 29 mA - 29 mA 29 mA
Prop。Delay @ Nom-Su - 3.8 ns - 3.8 ns 3.8 ns
propagation delay (tpd) - 3.4 ns - 3.4 ns 3.4 ns
Certification status - Not Qualified - Not Qualified Not Qualified
Schmitt trigger - NO - NO NO
Maximum seat height - 5.08 mm - 4.44 mm 4.57 mm
surface mount - NO - NO YES
technology - ECL - ECL ECL
Temperature level - OTHER - OTHER OTHER
Terminal form - THROUGH-HOLE - THROUGH-HOLE J BEND
Terminal pitch - 2.54 mm - 2.54 mm 1.27 mm
Terminal location - DUAL - DUAL QUAD
width - 7.62 mm - 7.62 mm 8.965 mm
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