PEEL18LV8ZT-15 datasheet, PDF - EEWORLD Datasheet

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PEEL18LV8ZT-15: DescriptionEE PLD, 15ns, PAL-Type, CMOS, PDSO20, 0.170 INCH, TSSOP-20; CategoryProgrammable logic devices Programmable logic; File Size111KB，10 Pages; ManufacturerIntegrated Circuit Systems（IDT ）

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PEEL18LV8ZT-15 Overview

EE PLD, 15ns, PAL-Type, CMOS, PDSO20, 0.170 INCH, TSSOP-20

PEEL18LV8ZT-15 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Parts packaging code	TSSOP
package instruction	TSSOP, TSSOP20,.25
Contacts	20
Reach Compliance Code	unknown
Architecture	PAL-TYPE
maximum clock frequency	31.25 MHz
JESD-30 code	R-PDSO-G20
JESD-609 code	e0
length	6.5 mm
Dedicated input times	9
Number of I/O lines	8
Number of entries	18
Output times	8
Number of product terms	113
Number of terminals	20
Maximum operating temperature	70 °C
Minimum operating temperature
organize	9 DEDICATED INPUTS, 8 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP20,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
power supply	3/3.3 V
Programmable logic type	EE PLD
propagation delay	15 ns
Certification status	Not Qualified
Maximum seat height	1.1 mm
Maximum supply voltage	3.6 V
Minimum supply voltage	2.7 V
Nominal supply voltage	3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
width	4.4 mm
Base Number Matches	1

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Commercial/Industrial

PEEL™ 18LV8Z-15 / I-15

CMOS Programmable Electrically Erasable Logic Device

Features

•

Low Voltage, Ultra Low Power Operation

- V

= 2.7 to 3.6 V

- I

= 5 µA (typical) at standby

- I

= 1.5 mA (typical) at 1 MHz

- Meets JEDEC LV Interface Spec (JEDSD8-A)

- 5 Volts tolerant inputs and I/O’s

CMOS Electrically Erasable Technology

- Superior factory testing

- Reprogrammable in plastic package

- Reduces retrofit and development costs

Application Versatility

- Replaces random logic

- Super set of standard PLDs

- Pin and JEDEC compatible with 16V8

- Ideal for battery powered systems

- Replaces expensive oscillators

•

Architectural Flexibility

- Enhanced architecture fits in more logic

- 113 product terms x 36 input AND array

- 10 inputs and 8 I/O pins

- 12 possible macrocell configurations

- Asynchronous clear, Synchronous preset

- Independent output enables

- Programmable clock; pin 1 or p-term

- Programmable clock polarity

- 20 Pin DIP/SOIC/TSSOP and PLCC

- Schmitt triggers on clock and data inputs

Schmitt Trigger Inputs

- Eliminates external Schmitt trigger devices

- Ideal for encoder designs

•

General Description

The PEEL18LV8Z is a Programmable Electrically Erasable

Logic (PEEL) SPLD (Simple Programmable Logic Device)

that operates over the supply voltage range of 2.7V-3.6V

and features ultra-low, automatic "zero" power-down

operation. The PEEL18LV8Z is logically and functionally

similar to ICT's 5V PEEL18CV8 and PEEL18CV8Z. The

"zero power" (25

µA

max. I

) power-down mode makes

the PEEL18LV8Z ideal for a broad range of battery-

powered portable equipment applications, from hand-held

meters to PCMCIA modems. EE-reprogrammability

provides both the convenience of fast reprogramming for

product development and quick product personalization in

manufacturing, including Engineering Change Orders.

The differences between the PEEL18LV8Z and

PEEL18CV8 include the addition of programmable clock

polarity, p-term clock, and Schmitt trigger input buffers on

all inputs, including the clock. Schmitt trigger inputs allow

direct input of slow or noisy signals.

Like the PEEL18CV8, the PEEL18LV8Z is a logical

superset of the industry standard PAL16V8 SPLD. The

PEEL18LV8Z provides additional architectural features that

allow more logic to be incorporated into the design. ICT's

JEDEC file translator allows easy conversion of existing 20

pin PLD designs to the PEEL18LV8Z architecture without

the need for redesign. The PEEL18LV8Z architecture

allows it to replace over twenty standard 20-pin DIP, SOIC,

TSSOP and PLCC packages Pin Configuration.

C LK M U X (O ptional)

I/C LK1

GN D

I/O

I/C LK1

GN D

C C

I/O

D IP

I/CLK1

VCC

I/O

TS S O P

I/C LK1

9 10 11 12 13

1 20 19

I/O

GN D

I/O

GND

I/O

P L C C -J

I/O

S O IC

Figure 1 - Pin Configuration

Figure 2 - Block Diagram

1 of 10

04-02-055A

PEEL18LV8ZT-15 Related Products

	PEEL18LV8ZT-15	PEEL18LV8ZJ-15
Description	EE PLD, 15ns, PAL-Type, CMOS, PDSO20, 0.170 INCH, TSSOP-20	EE PLD, 15ns, PAL-Type, CMOS, PQCC20, PLASTIC, LCC-20
Is it Rohs certified?	incompatible	incompatible
Parts packaging code	TSSOP	QLCC
package instruction	TSSOP, TSSOP20,.25	QCCJ, LDCC20,.4SQ
Contacts	20	20
Reach Compliance Code	unknown	unknown
Architecture	PAL-TYPE	PAL-TYPE
maximum clock frequency	31.25 MHz	31.25 MHz
JESD-30 code	R-PDSO-G20	S-PQCC-J20
JESD-609 code	e0	e0
length	6.5 mm	8.9662 mm
Dedicated input times	9	7
Number of I/O lines	8	10
Number of entries	18	18
Output times	8	8
Number of product terms	113	113
Number of terminals	20	20
Maximum operating temperature	70 °C	70 °C
organize	9 DEDICATED INPUTS, 8 I/O	7 DEDICATED INPUTS, 10 I/O
Output function	MACROCELL	MACROCELL
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSSOP	QCCJ
Encapsulate equivalent code	TSSOP20,.25	LDCC20,.4SQ
Package shape	RECTANGULAR	SQUARE
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	CHIP CARRIER
power supply	3/3.3 V	3/3.3 V
Programmable logic type	EE PLD	EE PLD
propagation delay	15 ns	15 ns
Certification status	Not Qualified	Not Qualified
Maximum seat height	1.1 mm	4.369 mm
Maximum supply voltage	3.6 V	3.6 V
Minimum supply voltage	2.7 V	2.7 V
Nominal supply voltage	3 V	3 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	GULL WING	J BEND
Terminal pitch	0.65 mm	1.27 mm
Terminal location	DUAL	QUAD
width	4.4 mm	8.9662 mm
Base Number Matches	1	1

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