UPD45128163G5-A75-9JF-E datasheet, PDF

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UPD45128163G5-A75-9JF-E: DescriptionSynchronous DRAM, 8MX16, 5.4ns, CMOS, PDSO54, ROHS COMPLIANT, PLASTIC, TSOP2-54; Categorystorage storage; File Size902KB，86 Pages; ManufacturerELPIDA; Websitehttp://www.elpida.com/en; Environmental Compliance

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UPD45128163G5-A75-9JF-E Overview

Synchronous DRAM, 8MX16, 5.4ns, CMOS, PDSO54, ROHS COMPLIANT, PLASTIC, TSOP2-54

UPD45128163G5-A75-9JF-E Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Parts packaging code	TSOP2
package instruction	TSOP2, TSOP54,.46,32
Contacts	54
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	5.4 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	133 MHz
I/O type	COMMON
interleaved burst length	1,2,4,8
JESD-30 code	R-PDSO-G54
length	22.22 mm
memory density	134217728 bit
Memory IC Type	SYNCHRONOUS DRAM
memory width	16
Number of functions	1
Number of ports	1
Number of terminals	54
word count	8388608 words
character code	8000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	8MX16
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP2
Encapsulate equivalent code	TSOP54,.46,32
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3.3 V
Certification status	Not Qualified
refresh cycle	4096
Maximum seat height	1.2 mm
self refresh	YES
Continuous burst length	1,2,4,8,FP
Maximum standby current	0.001 A
Maximum slew rate	0.24 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	10.16 mm
Base Number Matches	1

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DATA SHEET

MOS INTEGRATED CIRCUIT

PD45128163-E

128M-bit Synchronous DRAM

4-bank, LVTTL

Description

The

PD45128163 is high-speed 134,217,728-bit synchronous dynamic random-access memory, organized as

2,097,152

4 (word

bit

bank).

The synchronous DRAM achieved high-speed data transfer using the pipeline architecture.

All inputs and outputs are synchronized with the positive edge of the clock.

The synchronous DRAM is compatible with Low Voltage TTL (LVTTL).

This product is packaged in 54-pin TSOP (II).

Features

•

Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge

•

Pulsed interface

•

Possible to assert random column address in every cycle

•

Quad internal banks controlled by BA0(A13) and BA1(A12)

•

Byte control by LDQM and UDQM

•

Programmable Wrap sequence (Sequential / Interleave)

•

Programmable burst length (1, 2, 4, 8 and full page)

•

Programmable /CAS latency (2 and 3)

•

Automatic precharge and controlled precharge

•

CBR (Auto) refresh and self refresh

• ×16

organization

•

Single 3.3 V

0.3 V power supply

•

LVTTL compatible inputs and outputs

•

4,096 refresh cycles / 64 ms

•

Burst termination by Burst stop command and Precharge command

•

TSOP (II) package with lead free solder (Sn-Bi)



RoHS compliant

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for

availability and additional information.

Document No. E0728N10 (Ver.1.0)

Date Published June 2005 (K) Japan

Printed in Japan

URL: http://www.elpida.com

Elpida

Memory, Inc. 2005

Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.

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