MITSUBISHI LSIs
MITSUBISHI LSIs
M5M29FB/T800FP,VP,RV-80,-10,-12
M5M29FB/T800FP,VP,RV-80,-10,-12
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
DESCRIPTION
The MITSUBISHI M5M29FB/T800FP, VP, RV are 3.3V-only high speed 8,388,608-bit CMOS boot block Flash Memories suitable for
mobile and personal computing, and communication products. The M5M29FB/T800FP, VP, RV are fabricated by CMOS technology for
the peripheral circuits and DINOR(Divided bit line NOR) architecture for the memory cells, and are available in 44pin SOP or 48pin
TSOP(I).
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
FEATURES
.................................
524,288 word x 16bit
.................................
1,048,576 word x 8 bit
.............................
V
CC
= 3.3V±0.3V
Supply voltage
................................
..............................
80/100/120ns (Max)
Access time
Organization
Power Dissipation
.......................
108 mW (Max.)
Read
.......................
144 mW (Max.)
Program/Erase
.......................
0.72 mW (Max.)
Standby
Deep power down mode
.......................
3.3µW (typ.)
Auto program
.......................
7.5ms (typ.)
Program Time
.................................
128word
Program Unit
Auto Erase
.................................
50 ms (typ.)
Erase time
Erase Unit
Boot Block
.................................
8Kword / 16Kbyte x 1
........................
4Kword / 8Kbyte x 2
Parameter Block
.......................
16Kword / 32Kbyte x 1
Main Block
...........................
32Kword / 64Kbyte x 15
Program/Erase cycles
.......................................
100Kcycles
Boot Block
...........................
Bottom Boot
M5M29FB800
...........................
Top Boot
M5M29FT800
Other Functions
Software Command Control
Selective Block Lock
Erase Suspend/Resume
Program Suspend/Resume
Status Register Read
Sleep
Package
48-Lead, 12mmx 20mm TSOP (type-I)
44-Lead SOP
PIN CONFIGURATION (TOP VIEW)
ADDRESS
INPUTS
CHIP ENABLE
INPUT
NC
A
18
A
17
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
/CE
GND
/OE
DQ
0
DQ
8
DQ
1
DQ
9
DQ
2
DQ
10
DQ
3
DQ
11
1
2
3
4
5
6
44
43
42
41
40
39
/RP
RESET/
POWER DOWN
INPUT
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
/WE
WRITE ENABLE
INPUT
A
8
A
9
A
10
A
11
ADDRESS
A
12
INPUTS
A
13
A
14
A
15
A
16
/BYTE
BYTE ENABLE
INPUT
GND
DQ15/A-1
DQ
7
DQ
14
DQ
6
DQ
13
DQ
5
DQ
12
DQ
4
V
CC
DATA
INPUTS/
OUTPUTS
M5M29FB/T800FP
OUTPUT ENABLE
INPUT
DATA
INPUTS/
OUTPUTS
Outline 600mil 44-pin SOP
(FP: 44P2A-A)
APPLICATION
Code Storage PC BIOS
Digital Cellular Phone/Telecommunication
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
NC
NC
/WE
/RP
NC
/WP
RY/BY
A
18
A
17
A
7
A
6
A
5
A
4
A
3
A
2
A
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
M5M29FB/T800VP
37
36
35
34
33
32
31
30
29
28
27
26
25
A
16
/BYTE
GND
DQ
15
/A-1
DQ
7
DQ
14
DQ
6
DQ
13
DQ
5
DQ
12
DQ
4
V
CC
DQ
11
DQ
3
DQ
10
DQ
2
DQ
9
DQ
1
DQ
8
DQ
0
/OE
GND
/CE
A
0
A
16
/BYTE
GND
DQ
15
/A-1
DQ
7
DQ
14
DQ
6
DQ
13
DQ
5
DQ
12
DQ
4
V
CC
DQ
11
DQ
3
DQ
10
DQ
2
DQ
9
DQ
1
DQ
8
DQ
0
/OE
GND
/CE
A
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
M5M29FB/T800RV
37
36
35
34
33
32
31
30
29
28
27
26
25
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
NC
NC
/WE
/RP
NC
/WP
RY/BY
A
18
A
17
A
7
A
6
A
5
A
4
A
3
A
2
A
1
Outline 48pin TSOP type-I (12 X 20mm)
VP(Normal bend): 48P3R-B
RV(Reverse bend): 48P3R-C
NC : NO CONNECTION
This product is compatible with HN29WB/T800 by Hitachi Ltd.
1
May 1997 , Rev.6.1
MITSUBISHI LSIs
M5M29FB/T800FP,VP,RV-80,-10,-12
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
BLOCK DIAGRAM
A
18
A
17
A
16
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
/CE
/OE
/WE
/WP
/RP
/BYTE
RY/BY
128 WORD PAGE BUFFER
Boot Block
Parameter Block1
Parameter Block2
Main Block
Main Block
8KW
4KW
4KW
16KW
32KW
V
CC
(3.3V)
GND (0V)
X-DECODER
ADDRESS
INPUTS
Main Block
32KW
Y-DECODER
Y-GATE / SENSE AMP.
STATUS / ID REGISTER
MULTIPLEXER
CHIP ENABLE INPUT
OUTPUT ENABLE INPUT
WRITE ENABLE INPUT
WRITE PROTECT INPUT
RESET/POWER DOWN INPUT
BYTE ENABLE INPUT
READY/BUSY OUTPUT
CUI
WSM
INPUT/OUTPUT
BUFFERS
D
15
/A
-1
D
14
D
13
D
12
D
3
D
2
D
1
D
0
DATA INPUTS/OUTPUTS
FUNCTION
The M5M29FB/T800FP,VP,RV includes on-chip program/erase
control circuitry. The Write State Machine (WSM) controls block
erase and page program operations. Operational modes are
selected by the commands written to the Command User Interface
(CUI). The Status Register indicates the status of the WSM and
when the WSM successfully completes the desired program or
block erase operation.
A Deep Powerdown mode is enabled when the /RP pin is at GND,
minimizing power consumption.
Read
The M5M29FB/T800FP,VP,RV has three read modes, which
accesses to the memory array, the Device Identifier and the Status
Register. The appropriate read command are required to be
written to the CUI. Upon initial device powerup or after exit from
deep powerdown, the M5M29FB/T800 automatically resets to read
array mode. In the read array mode, low level input to /CE and
/OE, high level input to /WE and /RP, and address signals to the
address inputs (A0-A18) output the data of the addressed location
to the data input/output(D0-15).
Write
Writes to the CUI enables reading of memory array data, device
identifiers and reading and clearing of the Status Register. They
also enable block erase and program. The CUI is written by
bringing /WE to low level, while /CE is at low level and /OE is at
high level. Address and data are latched on the earlier rising edge
of /WE and /CE. Standard micro-processor write timings are used.
Output Disable
When /OE is at VIH, output from the devices is disabled.
Data input/output are in a high-impedance(High-Z) state.
Standby
When /CE is at VIH, the device is in the standby mode and its
power consumption is reduced. Data input/output are in a
high-impedance(High-Z) state. If the memory is deselected during
block erase or program, the internal control circuits remain active
and the device consume normal active power until the operation
completes.
Deep Power-Down
When /RP is at VIL, the device is in the deep powerdown
mode and its power consumption is substantially low. During
read modes, the memory is deselected and the data
input/output are in a high-impedance(High-Z) state. After
return from powerdown, the CUI is reset to Read Array , and
the Status Register is cleared to value 80H.
During block erase or program modes, /RP low will abort
either operation. Memory array data of the block being altered
become invalid.
2
May 1997 , Rev.6.1
MITSUBISHI LSIs
M5M29FB/T800FP,VP,RV-80,-10,-12
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
SOFTWARE COMMAND DEFINITIONS
The device operations are selected by writing specific software
command into the Command User Interface.
Read Array Command
(FFH)
The device is in Read Array mode on initial device powerup and
after exit from deep powerdown, or by writing FFH to the
Command User Interface. The device remains in Read Array
mode until the other commands are written.
Read Device Identifier Command
(90H)
Though PROM programmers can normally read device identifier
codes by raising A
9
to V
ID
, multiplexing high voltage onto address
lines is not desired for micro-processor system. It is an other
means to read device identifier codes that Read Device Identifier
Code Command(90H) is written to the command latch. Following
the command write, the manufacturer code and the device code
can be read from address 0000H and 0001H, respectively.
Read Status Register Command
(70H)
The Status Register is read after writing the Read Status Register
command of 70H to the Command User Interface.
The contents of Status Register are latched on the later falling
edge of /OE or /CE. So /CE or /OE must be toggled every status
read.
Clear Status Register Command
(50H)
The Erase Status and Program Status bits are set to "1"s by the
Write State Machine and can only be reset by the Clear Status
Register command of 50H. These bits indicates various failure
conditions.
Block Erase / Confirm Command
(20H/D0H)
Automated block erase is initiated by writing the Block Erase
command of 20H followed by the Confirm command of D0H. An
address within the block to be erased is required. The WSM
executes iterative erase pulse application and erase verify
operation.
Page Program Commands(41H)
Page Program allows fast programming of 128words of data.
Writing of 41H initiates the page program operation. From 2nd
cycle to 129th cycle write data must be serially inputted. Address
A6-0 have to be incremented from 00H to 7FH. After completion
of data loading, the WSM controls the program pulse application
and verify operation.
Basically re-program must not be done on a page which has
already programmed.
Suspend/Resume Command
(B0H/D0H)
Writing the Suspend command of B0H during block erase
operation interrupts the block erase operation and allows read out
from another block of memory. Writing the Suspend command of
B0H during program operation interrupts the program operation
and allows read out from another block of memory. The device
continues to output Status Register data when read, after the
Suspend command is written to it. Polling the WSM Status and
Suspend Status bits will determine when the erase operation or
program operation has been suspended. At this point, writing of
the Read Array command to the CUI enables reading data from
blocks other than that which is suspended. When the Resume
command of D0H is written to the CUI, the WSM will continue with
the erase or program processes.
DATA PROTECTION
The M5M29FB/T800 provides selectable block locking of memory
blocks. Each block has an associated nonvolatile lock-bit which
determines the lock status of the block.
In addition, the
M5M29FB/T800 has a master Write Protect pin (WP) which
prevents any modifications to memory blocks whose lock-bits are
set to "0", when /WP is low. When /WP is high or /RP is V
HH
, all
blocks can be programmed or erased regardless of the state of
the lock-bits, and the lock-bits are cleared to "1" by erase.
Power Supply Voltage
When the power supply voltage (Vcc) is less than 2.2V, the device
is set to the Read-only mode.
A delay time of 2 us is required before any device operation is
initiated. The delay time is measured from the time Vcc reaches
Vccmin (3.0V).
During power up, /RP=GND is recommended. Falling in Busy
status is not recommended for possibility of damaging the device.
3
May 1997 , Rev.6.1
MITSUBISHI LSIs
M5M29FB/T800FP,VP,RV-80,-10,-12
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
x8 ( Bytemode)
x16 ( Wordmode)
x8 ( Bytemode)
x16 ( Wordmode)
F0000H-FFFFFH 78000H-7FFFFH
E0000H-EFFFFH 70000H-77FFFH
D0000H-DFFFFH 68000H-6FFFFH
C0000H-CFFFFH 60000H-67FFFH
B0000H-BFFFFH 58000H-5FFFFH
A0000H-AFFFFH 50000H-57FFFH
90000H-9FFFFH 48000H-4FFFFH
80000H-8FFFFH 40000H-47FFFH
70000H-7FFFFH 38000H-3FFFFH
60000H-6FFFFH 30000H-37FFFH
50000H-5FFFFH 28000H-2FFFFH
40000H-4FFFFH 20000H-27FFFH
30000H-3FFFFH 18000H-1FFFFH
20000H-2FFFFH 10000H-17FFFH
10000H-1FFFFH 08000H-0FFFFH
08000H-0FFFFH 04000H-07FFFH
06000H-07FFFH 03000H-03FFFH
04000H-05FFFH 02000H-02FFFH
00000H-03FFFH 00000H-01FFFH
A
-1
-A
18
(Bytemode) A
0
-A
18
(Wordmode)
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
16Kword MAIN BLOCK
4Kword PARAMETER BLOCK
4Kword PARAMETER BLOCK
8Kword BOOT BLOCK
M5M29FB800 Memory Map
FC000H-FFFFFH 7E000H-7FFFFH
FA000H-FBFFFH 7D000H-7DFFFH
F8000H-F9FFFH 7C000H-7CFFFH
F0000H-F7FFFH 78000H-7BFFFH
E0000H-EFFFFH 70000H-77FFFH
D0000H-DFFFFH 68000H-6FFFFH
C0000H-CFFFFH 60000H-67FFFH
B0000H-BFFFFH 58000H-5FFFFH
A0000H-AFFFFH 50000H-57FFFH
90000H-9FFFFH 48000H-4FFFFH
80000H-8FFFFH 40000H-47FFFH
70000H-7FFFFH 38000H-3FFFFH
60000H-6FFFFH 30000H-37FFFH
50000H-5FFFFH 28000H-2FFFFH
40000H-4FFFFH 20000H-27FFFH
30000H-3FFFFH 18000H-1FFFFH
20000H-2FFFFH 10000H-17FFFH
10000H-1FFFFH 08000H-0FFFFH
00000H-0FFFFH 00000H-07FFFH
A
-1
-A
18
(Bytemode) A
0
-A
18
(Wordmode)
8Kword BOOT BLOCK
4Kword PARAMETER BLOCK
4Kword PARAMETER BLOCK
16Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
M5M29FT800 Memory Map
BUS OPERATIONS
Bus Operations for Word-Wide Mode (/
BYTE
=V
IH
)
Mode
Read
Pins
/CE
V
IL
V
IL
V
IL
V
IL
V
IL
V
IH
V
IL
V
IL
V
IL
X
/OE
V
IL
V
IL
V
IL
V
IL
V
IH
X
2)
V
IH
V
IH
V
IH
X
/WE
V
IH
V
IH
V
IH
V
IH
V
IH
X
V
IL
V
IL
V
IL
X
/RP
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IL
DQ
0-15
Data out
Status Register Data
Lock Bit Data (DQ
6
)
Identifier Code
Hi-Z
Hi-Z
Command/Data in
Command
Command
Hi-Z
RY/BY
V
OH (Hi-Z)
X
1)
X
V
OH (Hi-Z)
X
X
X
X
X
V
OH (Hi-Z)
Array
Status Register
Lock Bit Status
Identifier Code
Output disable
Stand by
Program
Write
Erase
Others
Deep Power Down
Bus Operations for Byte-Wide Mode (
BYTE
=V
IL
)
Mode
Pins
/CE
V
IL
V
IL
V
IL
V
IL
V
IL
V
IH
V
IL
V
IL
V
IL
X
/OE
V
IL
V
IL
V
IL
V
IL
V
IH
X
2)
V
IH
V
IH
V
IH
X
/WE
V
IH
V
IH
V
IH
V
IH
V
IH
X
V
IL
V
IL
V
IL
X
/RP
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IL
DQ
0-7
Data out
Status Register Data
Lock Bit Data (DQ
6
)
Identifier Code
Hi-Z
Hi-Z
Command/Data in
Command
Command
Hi-Z
RY/BY
V
OH (Hi-Z)
X
1)
X
V
OH (Hi-Z)
X
X
X
X
X
V
OH (Hi-Z)
Array
Read
Status Register
Lock Bit Status
Identifier Code
Output disable
Stand by
Program
Write
Erase
Others
Deep Power Down
1) X at RY/BY is V
OL
or V
OH(Hi-Z)
.
*The RY/BY is an open drain output pin and indicates status of the internal WSM. When low,it indicates that the WSM is Busy performing an operation.
A pull-up resistor of 10K-100K Ohms is required to allow the RY/BY signal to transition high indicating a Ready WSM condition.
2) X can be V
IH
or V
IL
for control pins.
4
May 1997 , Rev.6.1
MITSUBISHI LSIs
M5M29FB/T800FP,VP,RV-80,-10,-12
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
SOFTWARE COMMAND DEFINITION
Command List
Command
Read Array
Device Identifier
Read Status Register
Clear Status Register
Page Program
4)
Block Erase / Confirm
Suspend
Resume
Read Lock Bit Status
Lock Bit Program / Confirm
Erase All Unlocked Blocks
Sleep
7)
1st bus cycle
Mode
Address
Data
(D
7-0
)
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
X
X
X
X
X
X
X
X
X
X
X
X
FFH
90H
70H
50H
41H
20H
B0H
D0H
71H
77H
A7H
F0H
2nd bus cycle
Mode
Address
Data
(D
7-0
)
Read
Read
Write
Write
IA
2)
X
WA0
4)
BA
5)
ID
2)
SRD
3)
WD0
4)
D0H
Write
WA1
WD1
3rd bus cycle
Mode
Address
Data
(D
7-0
)
Read
Write
Write
BA
BA
X
DQ6
6)
D0H
D0H
1) In the word-wide mode, upper byte data (D8-D15) is ignored.
2) IA=ID Code Address : A0=VIL (Manufacturer's Code) : A0=VIH (Device Code), ID=ID Code,
/BYTE =VIL : A-1, A1-A18 = VIL, /BYTE =VIH : A1-A18 = VIL
3) SRD = Status Register Data
4) WA=Write Address, WD=Write Data.
/BYTE =VIL : Write Address and Write Data must be provided sequentially from 00H to FFH for A-1-A6.
Page size is 256Byte (256byte x 8bit), /BYTE =VIH : Write Address and Write Data must be provided
sequentially from 00H to 7FH for A0-A6. Page size is 128word (128word x 16bit).
5) BA = Block Address ( Addresses except Block Address mest be VIH.)
6) DQ6 provides Block Lock Status, DQ6 = 1 : Block Unlock, DQ6 = 0 : Block Locked.
7) Sleep command (F0H) put the device into the sleep mode after completing the current operation. The active current is reduced to deep power -down levels.
The Read Array command (FFH) must be written to get the device out of sleep mode.
BLOCK LOCKING
SOP Package
TSOP Package
/RP
V
IL
V
HH
V
IH
V
IH
Lock Bit(Internally)
X
X
0
1
/RP
V
IL
V
HH
V
IH
V
IH
V
IH
/WP
X
X
V
IL
V
IL
V
IH
Lock Bit(Internally)
X
X
0
1
X
Write Protection Provided
All Blocks Locked (Deep Power Down Mode)
All Blocks UnLocked
Blocks Locked (Depend on Lock Bit Data)
Blocks Unlocked (Depend on Lock Bit Data)
All Blocks Unlocked
D
6
provides Lock Status of each block after writing the Read Lock Status command (71H).
In case of TSOP package, /WP pin must not be switched during performing Read / Write operations or WSM Busy (WSMS = 0).
STATUS REGISTER
Symbol
SR.7
SR.6
SR.5
SR.4
SR.3
SR.2
SR.1
SR.0
(D
7
)
(D
6
)
(D
5
)
(D
4
)
(D
3
)
(D
2
)
(D
1
)
(D
0
)
Status
Write State Machine Status
Suspend Status
Erase Status
Program Status
Block Status after Program
Reserved
Reserved
Device Sleep Status
Definition
"1"
Ready
Suspended
Error
Error
Error
-
-
Device in Sleep
"0"
Busy
Operation in Progress / Completed
Successful
Successful
Successful
-
-
Device Not in Sleep
*The RY/BY is an open drain output pin and indicates status of the internal WSM. When low,it indicates that the WSM is Busy performing an operation.
A pull-up resistor of 10K-100K Ohms is required to allow the RY/BY signal to transition high indicating a Ready WSM condition.
*D3 indicates the block status after the page programming. When D3 is "1", the page has the over-programed cell . If over-program occures, the device is block
fail. However if D3 is "1", please try the block erase to the block. The block may revive.
DEVICE IDENTIFIER CODE
Code
Manufacturer Code
Device Code (-T)
Device Code (-B)
Pins
A
0
V
IL
V
IH
V
IH
D
7
0
0
0
D
6
0
1
1
D
5
0
0
0
D
4
1
1
1
D
3
1
1
1
D
2
1
1
1
D
1
0
0
1
D
0
0
1
0
Hex. Data
1CH
5DH
5EH
In the word-wide mode, the same data as D
7-0
is read out from D
15-8
.
A
9
= V
HH
Mode : A
9
= 11.5V~13.0V Set A9 to V
HH min.200ns before falling edge of /CE in ready status. Min.200ns after return to V
IH ,
device can't be accessed.
A
1
~A
8
, A
10
~A
18,
/CE,/OE = VIL, /WE = V
IH
D
15
/A
-1
= V
IL
(/BYTE = L)
5
May 1997 , Rev.6.1
京公网安备 11010802033920号
EEWORLD
