SN74LS122, SN74LS123
Retriggerable Monostable
Multivibrators
These dc triggered multivibrators feature pulse width control by
three methods. The basic pulse width is programmed by selection of
external resistance and capacitance values. The LS122 has an internal
timing resistor that allows the circuits to be used with only an external
capacitor. Once triggered, the basic pulse width may be extended by
retriggering the gated low-level-active (A) or high-level-active (B)
inputs, or be reduced by use of the overriding clear.
•
Overriding Clear Terminates Output Pulse
•
Compensated for VCC and Temperature Variations
•
DC Triggered from Active-High or Active-Low Gated Logic Inputs
•
Retriggerable for Very Long Output Pulses, up to 100% Duty Cycle
•
Internal Timing Resistors on LS122
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LOW POWER SCHOTTKY
PLASTIC
N SUFFIX
CASE 646
1
14
14
1
SOIC
D SUFFIX
CASE 751A
GUARANTEED OPERATING RANGES
Symbol
VCC
TA
IOH
IOL
Rext
Cext
Rext/Cext
Parameter
Supply Voltage
Operating Ambient
Temperature Range
Output Current – High
Output Current – Low
External Timing Resistance
External Capacitance
Wiring Capacitance at
Rext/Cext Terminal
5.0
Min
4.75
0
Typ
5.0
25
Max
5.25
70
–0.4
8.0
260
No Restriction
50
pF
16
1
Unit
V
°C
mA
mA
kW
16
1
16
1
PLASTIC
N SUFFIX
CASE 648
SOIC
D SUFFIX
CASE 751B
SOEIAJ
M SUFFIX
CASE 966
ORDERING INFORMATION
Device
SN74LS122N
SN74LS122D
SN74LS122DR2
SN74LS123N
SN74LS123D
SN74LS123DR2
SN74LS123M
SN74LS123MEL
Package
14 Pin DIP
SOIC–14
SOIC–14
16 Pin DIP
SOIC–16
SOIC–16
SOEIAJ–16
SOEIAJ–16
Shipping
2000 Units/Box
55 Units/Rail
2500/Tape & Reel
2000 Units/Box
38 Units/Rail
2500/Tape & Reel
See Note 1
See Note 1
1. For ordering information on the EIAJ version of
the SOIC package, please contact your local
ON Semiconductor representative.
©
Semiconductor Components Industries, LLC, 2001
1
October, 2001 – Rev. 7
Publication Order Number:
SN74LS122/D
SN74LS122, SN74LS123
LS122 FUNCTIONAL TABLE
INPUTS
CLEAR
L
X
X
X
H
H
H
H
H
H
H
↑
↑
A1
X
H
X
X
L
L
X
X
H
↓
↓
L
X
A2
X
H
X
X
X
X
L
L
↓
↓
H
X
L
B1
X
X
L
X
↑
H
↑
H
H
H
H
H
H
B2
X
X
X
L
H
↑
H
↑
H
H
H
H
H
OUTPUTS
Q
L
L
L
L
Q
H
H
H
H
CLEAR
L
X
X
H
H
↑
LS123 FUNCTIONAL TABLE
INPUTS
A
X
H
X
L
↓
L
B
X
X
L
↑
H
H
OUTPUTS
Q
L
L
L
Q
H
H
H
TYPICAL APPLICATION DATA
The output pulse tW is a function of the external
components, Cext and Rext or Cext and Rint on the LS122.
For values of Cext
≥
1000 pF, the output pulse at VCC = 5.0
V and VRC = 5.0 V (see Figures 1, 2, and 3) is given by
tW = K Rext Cext where K is nominally 0.45
If Cext is on pF and Rext is in kΩ then tW is in nanoseconds.
The Cext terminal of the LS122 and LS123 is an internal
connection to ground, however for the best system
performance Cext should be hard-wired to ground.
Care should be taken to keep Rext and Cext as close to the
monostable as possible with a minimum amount of
inductance between the Rext/Cext junction and the Rext/Cext
pin. Good groundplane and adequate bypassing should be
designed into the system for optimum performance to ensure
that no false triggering occurs.
It should be noted that the Cext pin is internally connected
to ground on the LS122 and LS123, but not on the LS221.
Therefore, if Cext is hard-wired externally to ground,
substitution of a LS221 onto a LS123 socket will cause the
LS221 to become non-functional.
The switching diode is not needed for electrolytic
capacitance application and should not be used on the LS122
and LS123.
To find the value of K for Cext
≥
1000 pF, refer to Figure 4.
Variations on VCC or VRC can cause the value of K to
change, as can the temperature of the LS123, LS122.
Figures 5 and 6 show the behavior of the circuit shown in
Figures 1 and 2 if separate power supplies are used for VCC
and VRC. If VCC is tied to VRC, Figure 7 shows how K will
vary with VCC and temperature. Remember, the changes in
Rext and Cext with temperature are not calculated and
included in the graph.
As long as Cext
≥
1000 pF and 5K
≤
Rext
≤
260K, the
change in K with respect to Rext is negligible.
If Cext
≤
1000 pF the graph shown on Figure 8 can be used
to determine the output pulse width. Figure 9 shows how K
will change for Cext
≤
1000 pF if VCC and VRC are connected
to the same power supply. The pulse width tW in
nanoseconds is approximated by
tW = 6 + 0.05 Cext (pF) + 0.45 Rext (kΩ) Cext + 11.6 Rext
In order to trim the output pulse width, it is necessary to
include a variable resistor between VCC and the Rext/Cext pin
or between VCC and the Rext pin of the LS122. Figure 10, 11,
and 12 show how this can be done. Rext remote should be
kept as close to the monostable as possible.
Retriggering of the part, as shown in Figure 3, must not
occur before Cext is discharged or the retrigger pulse will not
have any effect. The discharge time of Cext in nanoseconds
is guaranteed to be less than 0.22 Cext (pF) and is typically
0.05 Cext (pF).
For the smallest possible deviation in output pulse widths
from various devices, it is suggested that Cext be kept
≥
1000 pF.
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3
SN74LS122, SN74LS123
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Limits
Symbol
VIH
VIL
VIK
VOH
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
2.7
–0.65
3.5
0.25
VOL
Output LOW Voltage
0.35
Input HIGH Current
0.1
Input LOW Current
Short Circuit Current (Note 2)
LS122
ICC
Power Supply Current
LS123
20
–20
–0.4
–100
11
mA
VCC = MAX
0.5
20
IIH
IIL
IOS
V
µA
mA
mA
mA
0.4
Min
2.0
0.8
–1.5
Typ
Max
Unit
V
V
V
V
V
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
Guaranteed Input LOW Voltage for
All Inputs
VCC = MIN, IIN = –18 mA
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
IOL = 4.0 mA
IOL = 8.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
VCC = MAX, VIN = 2.7 V
VCC = MAX, VIN = 7.0 V
VCC = MAX, VIN = 0.4 V
VCC = MAX
2. Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS
(TA = 25°C, VCC = 5.0 V)
Limits
Symbol
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tW min
tWQ
Parameter
Pro agation
Propagation Delay, A to Q
Propagation Delay, A to Q
Pro agation
Propagation Delay, B to Q
Propagation Delay, B to Q
Pro agation
Propagation Delay, Clear to Q
Propagation Delay, Clear to Q
A or B to Q
A to B to Q
4.0
Min
Typ
23
32
23
34
28
20
116
4.5
Max
33
ns
45
44
ns
56
45
ns
27
200
5.0
ns
µs
Cext = 1000 pF, Rext = 10 kΩ,
F,
CL = 15 pF, RL = 2.0 kΩ
Cext = 0
CL = 15 pF
Rext = 5.0 kΩ
RL = 2.0 kΩ
Unit
Test Conditions
AC SETUP REQUIREMENTS
(TA = 25°C, VCC = 5.0 V)
Limits
Symbol
tW
Pulse Width
Parameter
Min
40
Typ
Max
Unit
ns
Test Conditions
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