Latch up Current...................................................... >200 mA
Operating Range
Range
Commercial
Industrial
Automotive-A
Ambient
Temperature
0°C to +70°C
–40°C to +85°C
–40°C to +85°C
V
CC
3.3V
±
10%
3.3V
±
10%
3.3V
±
10%
Electrical Characteristics
Over the Operating Range
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
Description
Test Conditions
–10 (Industrial/
Auto-A)
Min
Output HIGH Voltage V
CC
= Min.,
I
OH
= –4.0 mA
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[2]
Input Leakage Current GND < V
I
< V
CC
Output Leakage
Current
V
CC
Operating
Supply Current
Automatic CE
Power down Current
—TTL Inputs
Automatic CE
Power down Current
—CMOS Inputs
GND < V
I
< V
CC
,
Output Disabled
V
CC
= Max.,
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
Max. V
CC
, CE > V
IH
V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
Max. V
CC
,
CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V,
or V
IN
< 0.3V, f = 0
V
CC
= Min.,
I
OL
= 8.0 mA
2.0
–0.3
–1
–1
2.4
0.4
V
CC
+ 0.3
0.8
+1
+1
80
2.0
–0.3
–1
–1
Max
–12 (Industrial)
Min
2.4
0.4
V
CC
+ 0.3
0.8
+1
+1
75
2.0
–0.3
–1
–1
Max
–15 (Industrial)
Min
2.4
0.4
V
CC
+ 0.3
0.8
+1
+1
70
Max.
V
V
V
V
μA
μA
mA
Unit
I
SB1
15
15
15
mA
I
SB2
5
5
5
mA
Capacitance
[3]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
Max.
8
8
Unit
pF
pF
Notes
2. V
IL
(min.) = –2.0V for pulse durations of less than 20 ns.
3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05130 Rev. *G
Page 3 of 10
[+] Feedback
CY7C1019CV33
Figure 3. AC Test Loads and Waveforms
[4]
3.3V
OUTPUT
30 pF
R2 GND
351Ω
R 317Ω
3.0V
ALL INPUT PULSES
90%
10%
90%
10%
High-Z characteristics:
3.3V
OUTPUT
5 pF
R2
351Ω
R 317Ω
(a)
Rise Time: 1 V/ns
(b)
Fall Time: 1 V/ns
(c)
Switching Characteristics
Over the Operating Range
[5]
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
[8]
[8]
Description
-10 (Industrial/
Auto-A)
Min
Max
-12 (Industrial)
Min
12
Max
-15 (Industrial)
Min
15
Max
Unit
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
[6, 7]
CE LOW to Low Z
[7]
CE HIGH to High
Z
[6, 7]
CE LOW to Power Up
CE HIGH to Power Down
Write Cycle Time
CE LOW to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
Data Setup to Write End
Data Hold from Write End
WE HIGH to Low Z
[7]
WE LOW to High Z
[6, 7]
10
10
3
10
5
0
5
3
5
0
10
10
8
8
0
0
7
5
0
3
5
ns
15
ns
ns
15
7
ns
ns
ns
7
ns
ns
7
ns
ns
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
ns
12
3
12
6
0
6
3
6
0
12
12
9
9
0
0
8
6
0
3
6
15
10
10
0
0
10
8
0
3
0
3
0
3
Write Cycle
[9, 10]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Notes
4. AC characteristics (except High-Z) for all speeds are tested using the Thevenin load shown in section (a) in
Figure 3.
High-Z characteristics are tested for all
speeds using the test load shown in section (c) in
Figure 3.
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
6. t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (d) of
Figure 3.
Transition is measured
±500
mV from steady-state voltage.
7. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
8. This parameter is guaranteed by design and is not tested.
9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of
any of these signals can terminate the write. The input data setup and hold timing should be referenced to the leading edge of the signal that terminates the write.
10. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of t
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FPGA/CPLD
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