MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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by MC145444/D
MC145444
Advance Information
Single-Chip 300-Baud Modem
MC145444 is a silicon gate CMOS frequency shift keying (FSK) modem
intended for use with telemeter systems or remote control systems over the
telephone network.
This device is compatible with CCITT V.21 and contains the entire circuit that
provides a full–duplex or half–duplex 300–baud data communication over a pair
of telephone lines. This device also includes the DTMF generator and call
progress tone detector (CPTD).
The differential line driver has the capability of driving 0 dBm into a 600
Ω
load
with a single + 5 V power supply.
The transmit level is controlled by the programmable attenuator in 1 dB steps.
Devices functions are controlled through a 3–wire serial interface.
•
•
•
•
•
•
•
•
•
Capable of Driving 0 dBm into a 600
Ω
Load
DTMF Generator On–Chip
Imprecise Call Progress Detector On–Chip
A Transmit Attenuator Programmable in 1 dB Steps
3–Wire Serial Interface
Compatible with CCITT V.21
2100 Hz Answer Tone Generator On–Chip
Analog Loopback Configuration for Self Test
Simplex, Half–Duplex, and Full–Duplex Operation
1
20
H SUFFIX
PLASTIC DIP
CASE 804
20
DW SUFFIX
SOG PACKAGE
CASE 751D
1
ORDERING INFORMATION
MC145444P
Plastic DIP
MC145444DW SOG Package
PIN ASSIGNMENT
RxBO
FTLC
GNDA
CDA
GND
TLA
X1
X2
SD
RxD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
RxGC
RxA
TxA1
TxA2
DSI
VCC
ENB
SCK
DATA
TxD
This document contains information on a new product. Specifications and information herein are subject to change without notice.
REV 0
8/95
©
Motorola, Inc. 1995
MOTOROLA
MC145444
1
DC ELECTRICAL CHARACTERISTICS
(VCC = + 5.0 V
±
10%, TA = – 20 to + 70°C)
Characteristic
Input Voltage
H Level
L Level
Output Voltage
H Level
L Level
Input Current DATA, SCK, E, TxD
Quiescent Supply Current
Power–Down Supply Current
Symbol
VIH
VIL
VOH
VOL
Iin
ICC
ICC
ICC
IOH = 20
µA
IOL = 20
µA
IOL = 2 mA
Vin = VCC or GND
FSK Mode
Power–Down Mode 1
Power–Down Mode 2
Conditions
Min
3.15
—
VCC – 0.1
—
—
—
—
—
—
Typ
—
—
VCC – 0.01
0.01
—
±
1.0
8
—
—
Max
—
1.1
—
0.1
0.4
±
10.0
—
300
1
µA
mA
µA
µA
V
Unit
V
TRANSMIT CARRIER CHARACTERISTICS
(VCC = + 5.0 V
±
10%, TA = – 20 to + 70°C)
Characteristic
Carrier Frequency Channel 1
Mark ‘‘1’’
Space ‘‘0’’
Carrier Frequency Channel 2
Mark ‘‘1’’
Space ‘‘0’’
Answer Tone
Transmit Carrier Level
Second Harmonic Energy
Out–of–Band Energy
* VTXA1 – VTXA2, RL = 1.2 kΩ
Symbol
f1M
f1S
f2M
f2S
fans
VO*
V2h*
VOE*
Attenuator = 0 dB
RTLA =
∞
Crystal Frequency
C
lF
3.579545 MHz
Conditions
Min
974
1174
1644
1844
2094
—
—
Typ
980
1180
1650
1850
2100
6
– 46
Figure 1
Max
986
1186
1656
1856
2106
—
—
dBm
dBm
dBm
Unit
Hz
TRANSMIT ATTENUATOR CHARACTERISTICS
(VCC = + 5.0 V
±
10%, TA = – 20 to + 70°C)
Characteristic
Attenuator Range
Attenuator Accuracy
Symbol
ARNG
AACC
Conditions
Min
0
– 0.5
Typ
—
—
Max
15
+ 0.5
Unit
dB
dB
RECEIVER CHARACTERISTICS (Includes Hybrid, Demodulator and Carrier Detector)
(VCC = + 5.0 V
±
10%, TA = – 20 to + 70°C)
Characteristic
Input Impedance
Receiver Carrier Amplitude
Carrier Detect
Threshold
Hysterisis (VCDON – VCCDOF)
Carrier Detect Timing
OFF to ON
TCDON
OFF to ON
ON to OFF
Symbol
RIRX
VIRX
VCDON
VCDOF
HVS
CD1 = 0, CD0 = 0
CD1 = 0, CD0 = 1
CD1 = 0, CD1 = 1
CD1 = 1, CD0 = 1
ON to OFF
TCDOFF
CD1 = 0, CD0 = 0
CD1 = 0, CD0 = 1
CD1 = 0, CD0 = 1
CD1 = 1, CD0 = 1
CDA = 1.2 V
fin = 1.0 kHz
10
i
Conditions
RxA Pin (Pin 19)
Min
50
– 48
—
—
2
—
—
—
—
—
—
—
—
Typ
—
—
– 44
– 47
—
450
15
15
80
30
30
15
10
Max
—
– 12
—
—
—
—
—
—
—
—
—
—
—
dB
ms
Unit
kΩ
dBm
dBm
MOTOROLA
MC145444
3
BAND–PASS FILTER CHARACTERISTICS (RxA to FTLC)
(VCC = + 5.0 V
±
10%, TA = – 20 to + 70°C)
Characteristic
FTLC Output Impedance
Adjacent Channel Rejection
Pass–Band Gain
Group Delay
Symbol
ROFT
REJ
GPAS
Low–Band Filter
930 – 1230 Hz
High–Band Filter
1600 – 1900 Hz
VRXA = – 12 dBm
Conditions
Min
10
—
—
—
—
Typ
—
50
10
700
800
Max
50
—
—
—
—
Unit
kΩ
dB
dB
µs
DTMF CHARACTERISTICS
(VCC = + 5.0 V
±
10%, TA = – 20 to + 70°C)
Characteristic
Tone Output Level
Low Group
High Group
High Group Pre Emphasis
DTMF Distortion
DTMF Frequency Variation
Out–of–Band Energy
Setup Time
* VTXA1 – VTXA2, RL = 1.2 kΩ
Symbol
Vfl*
Vfh*
PE
DIST
∆f
V
VOE*
tosc
—
Attenuator = 0 dB
RTLA =
∞
Crystal Frequency
3.579545 MHz
Conditions
Min
—
—
0
—
–1
Typ
3
4
—
5
—
Figure 1
4
—
Max
—
—
3
—
1
dB
%
%
dB
ms
Unit
dBm
CPTD CHARACTERISTICS
(VCC = + 5.0 V
±
10%, TA = – 20 to + 70°C)
Characteristic
Band–Pass Filter Center Frequency
Band–Pass Filter – 3 dB Band Width
Tone Detect Level
OFF to ON
ON to OFF
Tone Detect Timing
OFF to ON
ON to OFF
Symbol
fc
∆
BW
VTDON
VTDOF
TTDON
TTDOF
CDA = 1 2 V
1.2
fin = 400 Hz
Conditions
Min
—
—
—
—
—
—
Typ
400
140
– 44
– 47
10
25
Max
—
—
—
—
—
—
ms
Unit
Hz
Hz
dBm
DEMODULATOR CHARACTERISTICS
(VCC = + 5.0 V
±
10%, TA = – 20 to + 70°C)
Characteristic
Bit Bias
Bit Error Rate
Symbol
ID
BER
Conditions
Input Level = – 24 dBm
Input Level = – 24 dBm
CCITT Line Simulation
511 Bit Pattern
S/N = 5 dB
Min
—
—
Typ
5
0.00001
Max
—
—
Unit
%
—
SWITCHING CHARACTERISTICS
(VCC = + 5.0 V
±
10%, TA = – 20 to + 70°C)
Characteristic
Setup Times
DATA to SCK
SCK to ENB
Hold Time
Recovery Time
Input Rise Time
Input Fall Time
Input Pulse Width
ENB, SCK
SCK to DATA
ENB to SCK
th
trec
tr
tf
tw
Symbol
tsu
Conditions
Min
50
50
50
50
—
—
50
Typ
—
—
—
—
—
—
—
Max
—
—
—
—
2
2
—
Unit
ns
ns
ns
ns
µs
µs
ns
MC145444
4
MOTOROLA
0
0
3.4 k 4 k
16 k
256 k
f (Hz)
DATA 50%
tsu
SCK
th
LAST
CLK
tsu
ENB
50%
PREVIOUS
DATA LATCHED
50%
FIRST
CLK
trec
— VCC
— GND
— VCC
— GND
— VCC
— GND
– 25
– 15 dB/OCT.
– 55
ENB
tr
50%
50%
tf
— VCC
— GND
Figure 1. Out–of–Band Energy
Figure 2. Switching Characteristics
ENB
Enable Input (Pin 14)
Data is loaded into the 15–bit shift register when this pin is
at a logic low. When this pin transitions from a logic high to
low, the data is transferred to the internal latch on the falling
edge of ENB. New data loaded into the shift register will not
affect the device operation until this pin transitions from high
to low. (See Figure 2.)
TxD
Transmit Data Input (Pin 11)
This pin is the transmit data input, The mark frequency is
generated when this pin is at the logic high level. The space
frequency is generated when the pin is at a logic low.
RxD
Receive Data Output (Pin 10)
This pin is the receive data output. A high logic level of this
pin indicates that the mark carrier frequency has been re-
ceived, and a low logic level indicates the space carrier fre-
quency has been received.
SD
Carrier/Call Progress Tone Detect (Pin 9)
This pin is the output from the carrier detector or call prog-
ress tone detector. This pin works as a carrier detector in the
FSK mode and as the call progress tone detector in the
CPTD mode. The output goes to a logic low level when the
input signal reaches the minimum threshold of the detect
level that is adjusted by the CDA voltage. When SD = H, the
receive data output (RxD) is clamped high to avoid errors
that may occur with loop noise. The SD pin is also clamped
high in the other modes except during the power–down
mode.
TxA1
Non–Inverting Transmit Analog Carrier Output (Pin 18)
This pin is the line driver non–inverting output of the FSK
and tone transmit analog signals. A + 6 dBm (max) differen-
tial output voltage can be obtained by connecting a 1.2 kΩ
load resistor between Tx1 and Tx2. Attention must be set so
as not to exceed this level when an external input is added
to the DSI pin. A telephone line (600
Ω)
is driven through an
external 600
Ω
resistor. In this case, the output level be-
comes about half of differential output.
PIN DESCRIPTION
VCC
Positive Power Supply (Pin 15)
This pin is normally tied to the + 5.0 V. A 0.1
µF
decoupling
capacitor should be used.
GND
Ground Pin (Pin 5)
This pin is normally tied to 0 V.
GNDA
Analog Ground (Pin 3)
Analog ground is internally biased to (VCC – VSS) / 2. It
should be tied to ground through a 0.1
µF
and 100
µF
capacitor.
X1
Crystal Oscillator Output (Pin 7)
Connecting a 3.579545 MHz
±
0.1% crystal between X1
and X2 will cause the transmit frequencies to be within
±
64 MHz of nominal. X1 is capable of driving several CMOS
gates. An external clock may be applied to X2. X1 should
then be left open.
X2
Crystal Oscillator Input (Pin 8)
Refer to X1.
SCK
Shift Resister Clock Input (Pin 13)
This pin is the clock input for the 15–bit shift register. Serial
data is loaded into the shift register on the rising edge of this
clock.
DATA
Serial Data Input (Pin 12)
This pin is the 15–bit serial data input. This data deter-
mines the mode, DTMF signal, transmit attenuation, carrier
detect time, channel, and transmit squelch.
MOTOROLA
MC145444
5
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