TMX32C6416EGLZ5E0 datasheet, PDF

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TMX32C6416EGLZ5E0: Description64-BIT, 75.18 MHz, OTHER DSP, PBGA532, 23 X 23 MM, 0.80 MM PITCH, PLASTIC, BGA-532; CategoryThe embedded processor and controller Microcontrollers and processors; File Size3MB，145 Pages; ManufacturerRochester Electronics; Websitehttps://www.rocelec.com/

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TMX32C6416EGLZ5E0 Overview

64-BIT, 75.18 MHz, OTHER DSP, PBGA532, 23 X 23 MM, 0.80 MM PITCH, PLASTIC, BGA-532

TMX32C6416EGLZ5E0 Parametric

Parameter Name	Attribute value
Parts packaging code	BGA
package instruction	FBGA,
Contacts	532
Reach Compliance Code	unknown
Address bus width	23
barrel shifter	NO
boundary scan	YES
maximum clock frequency	75.18 MHz
External data bus width	64
Format	FIXED POINT
Internal bus architecture	MULTIPLE
JESD-30 code	S-PBGA-B532
length	23 mm
low power mode	YES
Number of terminals	532
Package body material	PLASTIC/EPOXY
encapsulated code	FBGA
Package shape	SQUARE
Package form	GRID ARRAY, FINE PITCH
Certification status	COMMERCIAL
Maximum seat height	3.3 mm
Maximum supply voltage	1.26 V
Minimum supply voltage	1.14 V
Nominal supply voltage	1.2 V
surface mount	YES
technology	CMOS
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
width	23 mm
uPs/uCs/peripheral integrated circuit type	DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches	1

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TMS320C6414, TMS320C6415, TMS320C6416

FIXED POINT DIGITAL SIGNAL PROCESSORS

SPRS146J − FEBRUARY 2001 − REVISED NOVEMBER 2003

Table of Contents

revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

GLZ BGA package (bottom view) . . . . . . . . . . . . . . . . . . . . . . 5

description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

device characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

device compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

functional block and CPU (DSP core) diagram . . . . . . . . . . . 9

CPU (DSP core) description . . . . . . . . . . . . . . . . . . . . . . . . . 10

memory map summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

peripheral register descriptions . . . . . . . . . . . . . . . . . . . . . . . 15

EDMA channel synchronization events . . . . . . . . . . . . . . . . 28

interrupt sources and interrupt selector . . . . . . . . . . . . . . . . 30

signal groups description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

device configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

multiplexed pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

debugging considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

terminal functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

documentation support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

clock PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

general-purpose input/output (GPIO) . . . . . . . . . . . . . . . . . . 71

power-down mode logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

power-supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . .

power-supply decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IEEE 1149.1 JTAG compatibility statement . . . . . . . . . . . . .

EMIF device speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

bootmode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

absolute maximum ratings over operating case

temperature range . . . . . . . . . . . . . . . . . . . . . . . . . .

recommended operating conditions . . . . . . . . . . . . . . . .

electrical characteristics over recommended ranges of

supply voltage and operating case temperature .

recommended clock and control signal transition

behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

parameter measurement information . . . . . . . . . . . . . . . 79

input and output clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

asynchronous memory timing . . . . . . . . . . . . . . . . . . . . . 85

programmable synchronous interface timing . . . . . . . . 89

synchronous DRAM timing . . . . . . . . . . . . . . . . . . . . . . . . 94

HOLD/HOLDA timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

BUSREQ timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . 108

host-port interface (HPI) timing . . . . . . . . . . . . . . . . . . . 109

peripheral component interconnect (PCI) timing

[C6415 and C6416 only] . . . . . . . . . . . . . . . . . . . . 114

multichannel buffered serial port (McBSP) timing . . . . 117

UTOPIA slave timing [C6415 and C6416 only] . . . . . . 128

timer timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

general-purpose input/output (GPIO) port timing . . . . 132

JTAG test-port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

ADVANCE INFORMATION

POST OFFICE BOX 1443

•

HOUSTON, TEXAS 77251−1443

TMX32C6416EGLZ5E0 Related Products

	TMX32C6416EGLZ5E0	TMX32C6415EGLZ5E0	TMX32C6414EGLZ6E3
Description	64-BIT, 75.18 MHz, OTHER DSP, PBGA532, 23 X 23 MM, 0.80 MM PITCH, PLASTIC, BGA-532	64-BIT, 75.18 MHz, OTHER DSP, PBGA532, 23 X 23 MM, 0.80 MM PITCH, PLASTIC, BGA-532	64-BIT, 75.18 MHz, OTHER DSP, PBGA532, 23 X 23 MM, 0.80 MM PITCH, PLASTIC, BGA-532
Parts packaging code	BGA	BGA	BGA
package instruction	FBGA,	FBGA,	FBGA,
Contacts	532	532	532
Reach Compliance Code	unknown	unknown	unknown
Address bus width	23	23	23
barrel shifter	NO	NO	NO
boundary scan	YES	YES	YES
maximum clock frequency	75.18 MHz	75.18 MHz	75.18 MHz
External data bus width	64	64	64
Format	FIXED POINT	FIXED POINT	FIXED POINT
Internal bus architecture	MULTIPLE	MULTIPLE	MULTIPLE
JESD-30 code	S-PBGA-B532	S-PBGA-B532	S-PBGA-B532
length	23 mm	23 mm	23 mm
low power mode	YES	YES	YES
Number of terminals	532	532	532
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	FBGA	FBGA	FBGA
Package shape	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY, FINE PITCH	GRID ARRAY, FINE PITCH	GRID ARRAY, FINE PITCH
Certification status	COMMERCIAL	COMMERCIAL	COMMERCIAL
Maximum seat height	3.3 mm	3.3 mm	3.3 mm
Maximum supply voltage	1.26 V	1.26 V	1.44 V
Minimum supply voltage	1.14 V	1.14 V	1.36 V
Nominal supply voltage	1.2 V	1.2 V	1.4 V
surface mount	YES	YES	YES
technology	CMOS	CMOS	CMOS
Terminal form	BALL	BALL	BALL
Terminal pitch	0.8 mm	0.8 mm	0.8 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM
width	23 mm	23 mm	23 mm
uPs/uCs/peripheral integrated circuit type	DIGITAL SIGNAL PROCESSOR, OTHER	DIGITAL SIGNAL PROCESSOR, OTHER	DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches	1	1	-

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