CD4023BC Buffered Triple 3-Input NAND Gate
October 1987
Revised April 2002
CD4023BC
Buffered Triple 3-Input NAND Gate
General Description
These triple gates are monolithic complementary MOS
(CMOS) integrated circuits constructed with N- and P-
channel enhancement mode transistors. They have equal
source and sink current capabilities and conform to stan-
dard B series output drive. The devices also have buffered
outputs which improve transfer characteristics by providing
very high gain. All inputs are protected against static dis-
charge with diodes to V
DD
and V
SS
.
Features
s
Wide supply voltage range:
s
Low power TTL compatibility:
fan out of 2 driving 74L or 1 driving 74LS
s
5V–10V–15V parametric ratings
s
Symmetrical output characteristics
s
Maximum input leakage 1
µ
A at 15V over full
temperature range
3.0V to 15V
s
High noise immunity: 0.45 V
DD
(typ)
Ordering Code:
Order Number
CD4023BCM
CD4023BCS
CD4023BCN
Package Number
M14A
M14D
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” tot he ordering code.
Connection Diagram
Block Diagram
1
/
3
Device Shown
Top View
*All Inputs Protected by Standard CMOS Input Protection Circuit.
© 2002 Fairchild Semiconductor Corporation
DS005956
www.fairchildsemi.com
CD4023BC
Absolute Maximum Ratings
(Note 1)
(Note 2)
DC Supply Voltage (V
DD
)
Input Voltage (V
IN
)
Storage Temp. Range (T
S
)
Power Dissipation (P
D
)
Dual-In-Line
Small Outline
Lead Temperature (T
L
)
(Soldering, 10 seconds)
260
°
C
700 mW
500 mW
Recommended Operating
Conditions
DC Supply Voltage (V
DD
)
Input Voltage (V
IN
)
Operating Temperature Range (T
A
)
5 V
DC
to 15 V
DC
0 V
DC
to V
DD
V
DC
−
0.5 V
DC
to
+
18 V
DC
−
0.5 V
DC
to V
DD
+
0.5 V
DC
−
65
°
C to
+
150
°
C
−
55
°
C to
+
125
°
C
Note 1:
“Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed; they are not meant to imply that
the devices should be operated at these limits. The table of “Recom-
mended Operating Conditions” and “Electrical Characteristics” provides
conditions for actual device operation.
Note 2:
V
SS
=
0V unless otherwise specified.
DC Electrical Characteristics
(Note 3)
Symbol
I
DD
Parameter
Quiescent Device Current
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
OL
LOW Level Output Voltage V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
OH
HIGH Level Output Voltage V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
IL
LOW Level Input Voltage
V
DD
=5V,
V
O
=4.5V
V
DD
=10V,
V
O
=9.0V
V
DD
=15V,
V
O
=13.5V
V
IH
HIGH Level Input Voltage
V
DD
=5V,
V
O
=0.5V
V
DD
=10V,
V
O
=1.0V
V
DD
=15V,
V
O
=1.5V
I
OL
LOW Level Output Current V
DD
=5V,
V
O
=
0.4V
(Note 4)
I
OH
V
DD
=
10V, V
O
=
0.5V
V
DD
=
15V, V
O
=
1.5V
HIGH Level Output Current V
DD
=
5V, V
O
=
4.6V
(Note 4)
I
IN
Input Current
V
DD
=
10V, V
O
=
9.5V
V
DD
=
15V, V
O
=
13.5V
V
DD
=
15V, V
IN
=
0V
V
DD
=
15V, V
IN
=
15V
Note 3:
V
SS
=
0V unless otherwise specified.
Note 4:
I
OH
and I
OL
are tested one output at a time.
Conditions
−55°C
Min
Typ
0.25
0.5
1.0
0.05
0.05
0.05
4.95
9.95
14.95
1.5
|I
O
|<1µA
3.5
|I
O
|<1µA
7.0
11.0
0.64
1.6
4.2
−0.64
−1.6
−4.2
−0.1
0.1
3.0
4.0
3.5
7.0
11.0
0.51
1.3
3.4
−0.51
−1.3
−3.4
4.95
9.95
14.95
Min
+25°C
Typ
0.004
0.005
0.006
0
0
0
5
10
15
2
4
6
3
6
9
0.88
2.2
8
−0.88
−2.2
−8
−10
−
5
10
−
5
−0.1
0.1
1.5
3.0
4.0
Max
0.25
0.5
1.0
0.05
0.05
0.05
+125°C
Min
Max
7.5
15
30
0.05
0.05
0.05
4.95
9.95
14.95
1.5
3.0
4.0
3.5
7.0
11.0
0.36
0.90
2.4
−0.36
−0.90
−2.4
−1.0
1.0
Units
µA
V
V
V
V
mA
mA
µA
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2
CD4023BC
AC Electrical Characteristics
Symbol
t
PHL
Parameter
Propagation Delay, HIGH-to-LOW Level
(Note 5)
Conditions
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
Min
Typ
130
60
40
110
50
35
90
50
40
5
17
Max
250
100
70
250
100
70
200
100
80
7.5
pF
pF
ns
ns
ns
Units
T
A
=
25
°
C, C
L
=
50 pF, R
L
=
200k, unless otherwise specified
t
PLH
Propagation Delay, LOW-to-HIGH Level
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
t
THL
,
t
TLH
C
IN
C
PD
Transition Time
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
Average Input Capacitance
Power Dissipation Capacity (Note 6)
Any Input
Any Gate
Note 5:
AC Parameters are guaranteed by DC correlated testing.
Note 6:
C
PD
determines the no load AC power consumption of any CMOS device.
For complete explanation, see Family Characteristics Application Note AN-90.
3
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CD4023BC
Physical Dimensions
inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M14A
www.fairchildsemi.com
4
CD4023BC
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
5
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