The SN54/ 74LS114A offers common clock and common clear inputs and
individual J, K, and set inputs. These monolithic dual flip-flops are designed
so that when the clock goes HIGH, the inputs are enabled and data will be
accepted. The logic level of the J and K inputs may be allowed to change when
the clock pulse is HIGH and the bistable will perform according to the truth
table as long as minimum set-up times are observed. Input data is transferred
to the outputs on the negative-going edge of the clock pulse.
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
LOW POWER SCHOTTKY
LOGIC DIAGRAM
(Each Flip-Flop)
J SUFFIX
CERAMIC
CASE 632-08
14
Q
5(9)
6(8)
Q
1
CLEAR (CD)
TO
OTHER
FLIP FLOP
J
3(11)
13
CLOCK (CP)
4(10)
SET (SD)
K
2(12)
14
1
N SUFFIX
PLASTIC
CASE 646-06
14
1
D SUFFIX
SOIC
CASE 751A-02
ORDERING INFORMATION
MODE SELECT — TRUTH TABLE
INPUTS
OPERATING MODE
SD
Set
Reset (Clear)
*Undetermined
Toggle
Load “0” (Reset)
Load “1” (Set)
Hold
L
H
L
H
H
H
H
CD
H
L
L
H
H
H
H
J
X
X
X
h
l
h
l
K
X
X
X
h
h
l
l
Q
H
L
H
q
L
H
q
Q
L
H
H
q
H
L
q
3
OUTPUTS
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
LOGIC SYMBOL
4
10
* Both outputs will be HIGH while both SD and CD are LOW, but the output states
are unpredictable if SD and CD go HIGH simultaneously.
H, h = HIGH Voltage Level
L, I = LOW Voltage Level
X = Don’t Care
l, h (q) = Lower case letters indicate the state of the referenced input (or output)
l, h (q) =
one set-up time prior to the HIGH to LOW clock transition.
J
CP
SD
Q
5
11
J
CP
SD
Q
9
13
2
K
CD
Q
6
12
K
CD
Q
8
1
VCC = PIN 14
GND = PIN 7
FAST AND LS TTL DATA
5-193
SN54/74LS114A
GUARANTEED OPERATING RANGES
Symbol
VCC
TA
IOH
IOL
Supply Voltage
Operating Ambient Temperature Range
Output Current — High
Output Current — Low
Parameter
54
74
54
74
54, 74
54
74
Min
4.5
4.75
– 55
0
Typ
5.0
5.0
25
25
Max
5.5
5.25
125
70
– 0.4
4.0
8.0
Unit
V
°C
mA
mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Limits
Symbol
VIH
VIL
VIK
VOH
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54
74
54, 74
VOL
Output LOW Voltage
74
J, K
Set
Clear
Clock
IIH
Input HIGH Current
J, K
Set
Clear
Clock
J, K
Set
Clear, Clock
– 20
0.35
0.5
20
60
120
160
0.1
0.3
0.6
0.8
– 0.4
– 0.8
– 1.6
– 100
6.0
V
2.5
2.7
54
74
– 0.65
3.5
3.5
0.25
0.4
Min
2.0
0.7
0.8
– 1.5
Typ
Max
Unit
V
V
V
V
V
V
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
Guaranteed Input LOW Voltage for
All Inputs
VCC = MIN, IIN = – 18 mA
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
IOL = 4.0 mA
IOL = 8.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
µA
VCC = MAX, VIN = 2.7 V
mA
VCC = MAX, VIN = 7.0 V
IIL
IOS
ICC
Input LOW Current
mA
mA
mA
VCC = MAX, VIN = 0.4 V
VCC = MAX
VCC = MAX
Output Short Circuit Current (Note 1)
Power Supply Current
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS
(TA = 25°C, VCC = 5.0 V)
Limits
Symbol
fMAX
tPLH
tPHL
Parameter
Maximum Clock Frequency
Propagation Delay, Clock,
Clear, Set to Output
Min
30
Typ
45
15
15
20
20
Max
Unit
MHz
ns
ns
VCC = 5.0 V
CL = 15 pF
Test Conditions
AC SETUP REQUIREMENTS
(TA = 25°C, VCC = 5.0 V)
Limits
Symbol
tW
tW
ts
th
Parameter
Clock Pulse Width High
Clear, Set Pulse Width
Setup Time
Hold Time
Min
20
25
20
0
Typ
Max
Unit
ns
ns
ns
ns
VCC = 5.0 V
Test Conditions
FAST AND LS TTL DATA
5-194
Case 751A-02 D Suffix
14-Pin Plastic
SO-14
-A-
14
8
NOTES:
1.
DIMENSIONS A" AND B" ARE DATUMS AND
T" IS A DATUM SURFACE.
2.
DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
3.
4.
CONTROLLING DIMENSION: MILLIMETER.
DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
5.
MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
6.
751A 01 IS OBSOLETE, NEW STANDARD
751A 02.
-B-
1
7
P
7 PL
0.25 (0.010)
M
B
M
G
C
SEATING
PLANE
R X 45°
D
14 PL
0.25 (0.010)
M
K
T
B
S
M
F
J
A
S
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
8.55
3.80
1.35
0.35
0.40
8.75
4.00
1.75
0.49
1.25
INCHES
MIN
MAX
0.337
0.150
0.054
0.014
0.016
0.344
0.157
0.068
0.019
0.049
1.27 BSC
0.19
0.10
0
0.25
0.25
7
0.050 BSC
0.008
0.004
0
0.009
0.009
7
°
°
°
°
5.80
0.25
6.20
0.50
0.229
0.010
0.244
0.019
Case 632-08 J Suffix
14-Pin Ceramic Dual In-Line
-A-
14
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
-B-
1
7
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIM F MAY NARROW TO 0.76 (0.030) WHERE
THE LEAD ENTERS THE CERAMIC BODY.
5. 632 01 THRU 07 OBSOLETE, NEW STANDARD
C
L
632 08.
-T-
SEATING
PLANE
K
F
D
14 PL
0.25 (0.010)
M
G
T
A
S
N
J
14 PL
M
0.25 (0.010)
M
T
B
S
DIM
A
B
C
D
F
G
J
K
L
M
N
MILLIMETERS
MIN
MAX
19.05
6.23
3.94
0.39
1.40
19.94
7.11
5.08
0.50
1.65
INCHES
MIN
MAX
0.750
0.245
0.155
0.015
0.055
0.785
0.280
0.200
0.020
0.065
2.54 BSC
0.21
3.18
0.38
4.31
0.100 BSC
0.008
0.125
0.015
0.170
7.62 BSC
0
°
15
°
0.300 BSC
0
°
15
°
0.51
1.01
0.020
0.040
Case 646-06 N Suffix
14-Pin Plastic
NOTES:
1.
LEADS WITHIN 0.13 mm (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
14
8
B
1
7
2.
DIMENSION L" TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3.
DIMENSION B" DOES NOT INCLUDE MOLD
FLASH.
4.
5.
ROUNDED CORNERS OPTIONAL.
646 05 OBSOLETE, NEW STANDARD 646 06.
A
F
C
N
H
G
D
SEATING
PLANE
NOTE 4
L
J
K
M
DIM
A
B
C
D
F
G
H
J
K
L
M
N
MILLIMETERS
MIN
MAX
18.16
6.10
3.69
0.38
1.02
19.56
6.60
4.69
0.53
1.78
INCHES
MIN
MAX
0.715
0.240
0.145
0.015
0.040
0.770
0.260
0.185
0.021
0.070
2.54 BSC
1.32
0.20
2.92
2.41
0.38
3.43
0.100 BSC
0.052
0.008
0.115
0.095
0.015
0.135
7.62 BSC
0
°
10
°
0.300 BSC
0
°
10
°
0.39
1.01
0.015
0.039
FAST AND LS TTL DATA
5-195
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
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applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does
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associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
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