1
TC835
PERSONAL COMPUTER DATA ACQUISITION A/D CONVERTER
FEATURES
s
s
s
s
s
s
s
s
Upgrade of Pin-Compatible TC7135, ICL7135,
MAX7135 and SI7135
Guaranteed 200 kHz Operation
Single 5V Operation With TC7660
Multiplexed BCD Data Output
UART and Microprocessor Interface
Control Outputs for Auto-Ranging
Input Sensitivity ............................................ 100
µ
V
No Sample and Hold Required
GENERAL DESCRIPTION
The TC835 is a low-power, 4-1/2 digit (0.005% resolu-
tion), BCD analog-to-digital converter (ADC) that has been
characterized for 200 kHz clock rate operation. The five
conversions per second rate is nearly twice as fast as the
ICL7135 or TC7135. The TC835 (like the TC7135) does
not use the external diode-resistor roll-over error compen-
sation circuits required by the ICL7135.
The multiplexed BCD data output is perfect for interfac-
ing to personal computers. The low-cost, greater than 14-
bit high-resolution, and 100
µV
sensitivity makes the TC835
exceptionally cost-effective.
Microprocessor-based data acquisition systems are
supported by the BUSY and STROBE outputs, along with
the RUN/HOLD input of the TC835. The overrange, under-
range, busy, and run/hold control functions and multiplexed
BCD data outputs make the TC835 the ideal converter for
µP-based
scales and measurement systems and intelligent
panel meters.*
The TC835 interfaces with full-function LCD and LED
display decoder/drivers. The UNDERRANGE and
OVERRANGE outputs may be used to implement an auto-
ranging scheme or special display functions.
*See Application Notes 16 and 17 for microprocessor interface tech-
niques.
2
3
4
5
6
APPLICATIONS
s
s
s
Personal Computer Data Acquisition
Scales, Panel Meters, Process Controls
HP-IL Bus Instrumentation
ORDERING INFORMATION
Part No.
TC835CBU
TC835CKW
TC835CPI
Package
64-Pin PQFP
44-Pin PQFP
28-Pin Plastic DIP
Temperature
Range
0°C to +70°C
0°C to +70°C
0°C to +70°C
NOTE:
Tape and reel available for 44-pin PQFP packages.
TYPICAL APPLICATION
ADDRESS BUS
CONTROL
DATA BUS
+ 5V
V+ REF
CAP
BUF
AZ
GAIN: 10, 20, 50, 100
+15V –15V
PA0
PA1
PA2
1Y
2Y
3Y
157
10
14
LH0084
16
–
6522
-VIA-
PA3
PA4
PA5
PA6
PA7
CA1
CA2
fIN
B1
D1
VR
D2
– INPUT
D3
D4
ANALOG
STB COMMON
R/H
DGND
fIN
GAIN SELECTION
– 5V
REF
VOLTAGE
PB0 PB1 PB2
PB5
PB4
PB3
CHANNEL SELECTION
TELCOM SEMICONDUCTOR, INC.
+
15
1B
2B
3B
SEL
1A
2A
3A
POL
OR
INT
UR
D5
B8
TC835
B4
+ INPUT
B2
11
8
3
9
DG529
DA
DB
WR
A1 A0 EN
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
DIFFERENTIAL
MULTIPLEXER
7
8
TC835-8 11/5/96
3-65
PERSONAL COMPUTER
DATA ACQUISITION A/D CONVERTER
TC835
ABSOLUTE MAXIMUM RATINGS*
(Note 1)
Positive Supply Voltage ............................................. +6V
Negative Supply Voltage ............................................ - 9V
Analog Input Voltage (Pin 9 or 10) ........ V
+
to V
–
(Note 2)
Reference Input Voltage (Pin 2) .......................... V
+
to V
–
Clock Input Voltage ............................................. 0V to V
+
Operating Temperature Range .................... 0°C to +70°C
Storage Temperature Range ................ – 65°C to +150°C
Lead Temperature (Soldering, 10 sec) ................. +300°C
Package Power Dissipation (T
A
≤
70°C)
28-Pin Plastic DIP ............................................. 1.14W
44-Pin PQFP .................................................... 1.00W
64-Pin PFP .......................................................1.14W
*Static-sensitive device. Unused devices must be stored in conductive
material. Protect devices from static discharge and static fields. Stresses
above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those
indicated in the operational sections of the specifications is not implied.
Exposure to Absolute Maximum Rating Conditions for extended periods
may affect device reliability.
ELECTRICAL CHARACTERISTICS:
T
A
= +25°C, f
CLOCK
= 200 kHz, V
+
= +5V, V
–
= – 5V, unless otherwise specified.
Symbol Parameter
Analog
Display Reading With
Zero Volt Input
Zero Reading
Temperature Coefficient
Full-Scale
Temperature Coefficient
Nonlinearity Error
Differential Linearity Error
Display Reading in
Ratiometric Operation
±
Full-Scale Symmetry
Error (Roll-Over Error)
Input Leakage Current
Noise
Input Low Current
Input High Current
Output Low Voltage
Output High Voltage
B
1
, B
2
, B
4
, B
8
, D
1
–D
5
Busy, Polarity, Overrange,
Underrange, Strobe
Clock Frequency
Notes 3 and 4
V
IN
= 0V
Note 5
V
IN
= 2V
Notes 5 and 6
Note 7
Note 7
V
IN
= V
REF
Note 3
–V
IN
= +V
IN
Note 8
Note 4
Peak-to-Peak Value Not Exceeded 95% of Time
V
IN
= 0V
V
IN
= +5V
I
OL
= 1.6 mA
I
OH
= 1 mA
I
OH
= 10
µA
Note 10
–0.0000
—
—
—
—
+0.9996
—
—
—
—
—
—
2.4
4.9
0
4
–3
—
—
—
±0.0000
0.5
—
0.5
0.01
+0.9998
0.5
1
15
10
0.08
0.2
4.4
4.99
200
5
–5
1
0.7
8.5
+0.0000
2
5
1
—
+1.0000
1
10
—
100
10
0.4
5
5
1200
6
–8
3
3
30
Display
Reading
µV/°C
ppm/°C
Count
LSB
Display
Reading
Count
pA
µV
P-P
µA
µA
V
V
V
kHz
V
V
mA
mA
mW
Test Conditions
Min
Typ
Max
Unit
TC
Z
TC
FS
NL
DNL
±FSE
I
IN
e
N
Digital
I
IL
I
IH
V
OL
V
OH
f
CLK
Power Supply
V
+
Positive Supply Voltage
V
–
Negative Supply Voltage
I
+
Positive Supply Current
–
I
Negative Supply Current
PD
Power Dissipation
NOTES:
f
CLK
= 0 Hz
f
CLK
= 0 Hz
f
CLK
= 0 Hz
1. Functional operation is not implied.
2. Limit input current to under 100
µA
if input voltages exceed supply
voltage.
3. Full-scale voltage = 2V.
4. V
IN
= 0V.
5. 0°C
≤
T
A
≤
+70°C.
6. External reference temperature coefficient less than 0.01 ppm/°C.
7. – 2V
≤
V
IN
≤
+2V. Error of reading from best fit straight
line.
8. |V
IN
| = 1.9959.
9. Test circuit shown in Figure 1.
10. Specification related to clock frequency range over which
the TC835 correctly performs its various functions.
Increased errors result at higher operating frequencies.
3-66
TELCOM SEMICONDUCTOR, INC.
PERSONAL COMPUTER
DATA ACQUISITION A/D CONVERTER
TC835
PIN CONFIGURATIONS
ANALOG COM
1
STROBE
2
NC
35
34
REF IN
OR
NC
NC
NC
UR
V–
REF IN
ANALOG
COM
INT OUT
AZ IN
BUFF OUT
–
C REF
+
CREF
– INPUT
1
2
3
4
5
6
7
8
9
28 UNDERRANGE
27
OVERRANGE
NC
1
INT OUT
2
AZ IN
3
BUFF OUT
4
REF CAP–
5
REF CAP+
6
–INPUT
+INPUT
7
8
44 43
42
41 40 39
38
37
36
NC
33
NC
32
NC
31
RUN/HOLD
30
DGND
29
POLARITY
26 STROBE
25 RUN/HOLD
24 DIGTAL GND
23 POLARITY
V–
3
4
5
TC835CPI
22 CLOCK IN
21 BUSY
20 D1 (LSD)
19 D2
18 D3
17 D4
16 B8 (MSD)
15 B4
TC835CKW
28
CLK IN
27
BUSY
26
D1 (LSD)
25
D2
24
NC
23
NC
+INPUT 10
V + 11
(MSD) D5 12
(LSB) B1 13
B2 14
V+
9
NC
10
NC
11
12 13
14
15 16
17
18
19
20
21 22
(MSD) D5
(LSB) B1
(MSB) B8
B2
B4
D4
NC
NC
D3
NC
RUN/HOLD
STROBE
CLK IN
DGND
BUSY
SUB
POL
NC
NC
NC
NC
NC
D1
64
63 62
61 60
59 58
57 56
55 54
53 52
51
50 49
D2
NC
NC
NC
1
NC
2
NC
3
NC
4
NC
5
NC
6
48
NC
47
NC
46
NC
45
D3
44
D4
43
B3
42
B4
41
B2
NC
OVERRANGE
7
UNDERRANGE
8
SUB
9
V–
10
REF IN
11
ANALOG COM
12
NC
13
NC
14
NC
15
NC
16
6
7
TC835CBU
NOTES 1 & 2
40
SUB
39
B1
38
D5
37
NC
36
NC
35
NC
34
NC
33
NC
17 18
19 20
21 22
23
24 25 26
27 28
29 30
31 32
BUF CAP–
BUF CAP+
INT OUT
AZ IN
NC
SUB
NC
NC
NC
–INPUT
NC
NC
BUFFOUT
+INPUT
NC
V+
NOTES:
1. NC = No internal connection.
2. Pins 9, 25, 40 and 56 are connected to the die substrate.
The potential at these pins is approximately V+. No
external connections should be made.
8
3-67
TELCOM SEMICONDUCTOR, INC.
PERSONAL COMPUTER
DATA ACQUISITION A/D CONVERTER
TC835
–5V
1
2
V–
REF IN
28
27
26
25
24
23
22
21
20
19
18
17
16
15
– IN
ANALOG
COM
SW I
SW1
SWITCH OPEN
SWITCH CLOSED
REF
IN
SWR
CREF
SW I
+ IN
–
SW RI
SW +
RI
SET VREF = 1V
VREF IN
100 kΩ
UNDERRANGE
ANALOG
INPUT BUFFER
+
–
CSZ
SWIZ
SWZ
COMPARATOR
+
–
RINT
CINT
SWZ
SW +
RI
–
SW RI
SWZ
INTEGRATOR
13
14
B1 (LSB)
B2
(MSB) B8
B4
Figure 1. Test Circuit
Figure 3B. System Zero Phase
V+
+ IN
SW I
ANALOG
INPUT BUFFER
+
–
SW RI
SW +
RI
–
CSZ
SWIZ
SWZ
COMPARATOR
+
–
RINT
CINT
LOGIC
INPUT
SWZ
ANALOG
COM
SW I
– IN
SW +
RI
–
SW RI
SWZ
INTEGRATOR
SW1
SWITCH OPEN
SWITCH CLOSED
Figure 2. Digital Logic Input
ANALOG
INPUT BUFFER
+
–
SW RI
SW +
RI
–
CSZ
SWIZ
REF
IN
SWR
CREF
SWZ
COMPARATOR
+
REF
IN
SWR
SW I
Figure 3C. Input Signal Integration Phase
ANALOG
INPUT BUFFER
+
–
SW RI
SW +
RI
–
CSZ
SWIZ
CREF
SWZ
COMPARATOR
+
–
RINT
CINT
SW I
+ IN
RINT
CINT
+ IN
SWZ
ANALOG
COM
SW I
– IN
SW +
RI
–
SW RI
SWZ
INTEGRATOR
TO
DIGITAL
SECTION
SWZ
ANALOG
COM
SW I
– IN
SW +
RI
–
SW RI
SWZ
INTEGRATOR
SW1
SW1
SWITCH OPEN
SWITCH CLOSED
Figure 3A. Analog Circuit Function Diagram
3-68
Figure 3D. Reference Voltage Integration Cycle
TELCOM SEMICONDUCTOR, INC.
–
–
+
BUFFER
REF
IN
SWR
CREF
–
CLOCK
INPUT
120 kHz
+
TO
DIGITAL
SECTION
OVERRANGE
3 ANALOG
STROBE
COMMON
ANALOG GND
4
RUN/HOLD
INT OUT
0.47
1 µF
5
µF
DIGTAL GND
AZ IN
6
POLARITY
BUFF OUT
100 kΩ
7
–
CLOCK IN
CREF
100
SIGNAL
1 µF 8
+
BUSY
kΩ
INPUT
CREF
9
–INPUT
(LSD) D1
0.1 µF
10
D2
+INPUT
TC835
11
+
D3
+5V
V
12 D5 (MSD)
D4
TO
DIGITAL
SECTION
+
TO
DIGITAL
SECTION
–
+
–
PERSONAL COMPUTER
DATA ACQUISITION A/D CONVERTER
TC835
SW I
+ IN
–
SW RI
SW +
RI
ANALOG
INPUT BUFFER
+
–
CSZ
SWIZ
REF
IN
SWR
CREF
SWZ
COMPARATOR
+
–
RINT
CINT
1
The dual-slope converter accuracy is unrelated to the
integrating resistor and capacitor values, as long as they are
stable during a measurement cycle. An inherent benefit is
noise immunity. Noise spikes are integrated, or averaged, to
zero during the integration periods. Integrating ADCs are
immune to the large conversion errors that plague succes-
sive approximation converters in high-noise environments.
(See Figure 4.)
2
3
4
5
SWZ
ANALOG
COM
SW I
– IN
SW +
RI
–
SW RI
SWZ
INTEGRATOR
SW1
SWITCH OPEN
SWITCH CLOSED
Figure 3E. Integrator Output Zero Phase
GENERAL THEORY OF OPERATION
(All Pin Designations Refer to 28-Pin DIP)
Dual-Slope Conversion Principles
The TC835 is a dual-slope, integrating analog-to-digital
converter. An understanding of the dual-slope conversion
technique will aid in following the detailed TC835 opera-
tional theory.
The conventional dual-slope converter measurement
cycle has two distinct phases:
(1) Input signal integration
(2) Reference voltage integration (deintegration)
The input signal being converted is integrated for a fixed
time period. Time is measured by counting clock pulses. An
opposite polarity constant reference voltage is then inte-
grated until the integrator output voltage returns to zero. The
reference integration time is directly proportional to the input
signal.
In a simple dual-slope converter, a complete conversion
requires the integrator output to "ramp-up" and "ramp-
down."
A simple mathematical equation relates the input signal,
reference voltage, and integration time:
1
RC
SWITCH
DRIVER
REF
VOLTAGE
PHASE
CONTROL CONTROL
LOGIC
POLARITY CONTROL
INTEGRATOR
OUTPUT
DISPLAY
VIN
VIN
VARIABLE
REFERENCE
INTEGRATE
TIME
∫
0
t
SI
V
IN
(t) dt =
V
R
t
RI
RC
,
VFULL SCALE
1/2 VFULL SCALE
where:
V
R
= Reference voltage
t
SI
= Signal integration time (fixed)
t
RI
= Reference voltage integration time (variable).
For a constant V
IN
:
V
IN
= V
R
FIXED
SIGNAL
INTEGRATE
TIME
Figure 4. Basic Dual-Slope Converter
[ ]
t
RI
t
SI
.
3-69
TELCOM SEMICONDUCTOR, INC.
+
–
+
–
–
+
TO
DIGITAL
SECTION
TC835 Operational Theory
The TC835 incorporates a system zero phase and
integrator output voltage zero phase to the normal two-
phase dual-slope measurement cycle. Reduced system
errors, fewer calibration steps, and a shorter overrange
recovery time result.
The TC835 measurement cycle contains four phases:
(1)
(2)
(3)
(4)
System zero
Analog input signal integration
Reference voltage integration
Integrator output zero
Internal analog gate status for each phase is shown in
Table 1.
ANALOG
INPUT
SIGNAL
INTEGRATOR
COMPARATOR
CLOCK
6
7
COUNTER
8
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