PR ELIMIN A RY
LM3S1138 Microcontroller
DATA SHE ET
DS-LM3S1138- 15 8 2
Copyright
©
2007 Luminary Micro, Inc.
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Copyright
©
2007 Luminary Micro, Inc. All rights reserved. Stellaris is a registered trademark and Luminary Micro and the Luminary Micro logo are
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Preliminary
September 02, 2007
LM3S1138 Microcontroller
Table of Contents
About This Document .................................................................................................................... 18
Audience ..............................................................................................................................................
About This Manual ................................................................................................................................
Related Documents ...............................................................................................................................
Documentation Conventions ..................................................................................................................
18
18
18
18
20
25
25
26
27
27
28
28
30
30
31
32
34
34
34
35
35
35
35
35
1
1.1
1.2
1.3
1.4
1.4.1
1.4.2
1.4.3
1.4.4
1.4.5
1.4.6
1.4.7
1.4.8
Architectural Overview ...................................................................................................... 20
Product Features ......................................................................................................................
Target Applications ....................................................................................................................
High-Level Block Diagram .........................................................................................................
Functional Overview ..................................................................................................................
ARM Cortex™-M3 .....................................................................................................................
Motor Control Peripherals ..........................................................................................................
Analog Peripherals ....................................................................................................................
Serial Communications Peripherals ............................................................................................
System Peripherals ...................................................................................................................
Memory Peripherals ..................................................................................................................
Additional Features ...................................................................................................................
Hardware Details ......................................................................................................................
Block Diagram ..........................................................................................................................
Functional Description ...............................................................................................................
Serial Wire and JTAG Debug .....................................................................................................
Embedded Trace Macrocell (ETM) .............................................................................................
Trace Port Interface Unit (TPIU) .................................................................................................
ROM Table ...............................................................................................................................
Memory Protection Unit (MPU) ...................................................................................................
Nested Vectored Interrupt Controller (NVIC) ................................................................................
2
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
ARM Cortex-M3 Processor Core ...................................................................................... 33
3
4
5
5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.3
5.4
5.4.1
5.4.2
Memory Map ....................................................................................................................... 39
Interrupts ............................................................................................................................ 41
JTAG Interface .................................................................................................................... 44
Block Diagram ..........................................................................................................................
Functional Description ...............................................................................................................
JTAG Interface Pins ..................................................................................................................
JTAG TAP Controller .................................................................................................................
Shift Registers ..........................................................................................................................
Operational Considerations ........................................................................................................
Initialization and Configuration ...................................................................................................
Register Descriptions ................................................................................................................
Instruction Register (IR) .............................................................................................................
Data Registers ..........................................................................................................................
45
45
46
47
48
48
51
51
51
53
6
6.1
6.1.1
6.1.2
System Control ................................................................................................................... 55
Functional Description ............................................................................................................... 55
Device Identification .................................................................................................................. 55
Reset Control ............................................................................................................................ 55
September 02, 2007
Preliminary
3
Table of Contents
6.1.3
6.1.4
6.1.5
6.2
6.3
6.4
Power Control ...........................................................................................................................
Clock Control ............................................................................................................................
System Control .........................................................................................................................
Initialization and Configuration ...................................................................................................
Register Map ............................................................................................................................
Register Descriptions ................................................................................................................
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
Register Access Timing ...........................................................................................................
Clock Source ..........................................................................................................................
Battery Management ...............................................................................................................
Real-Time Clock ......................................................................................................................
Non-Volatile Memory ...............................................................................................................
Power Control .........................................................................................................................
Interrupts and Status ...............................................................................................................
Initialization and Configuration .................................................................................................
Initialization .............................................................................................................................
RTC Match Functionality (No Hibernation) ................................................................................
RTC Match/Wake-Up from Hibernation .....................................................................................
External Wake-Up from Hibernation ..........................................................................................
RTC/External Wake-Up from Hibernation ..................................................................................
Register Map ..........................................................................................................................
Register Descriptions ..............................................................................................................
58
58
60
61
61
62
7
7.1
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.4
7.5
Hibernation Module .......................................................................................................... 114
115
115
115
116
116
116
117
117
117
118
118
118
118
119
119
119
120
8
8.1
8.2
8.2.1
8.2.2
8.3
8.3.1
8.3.2
8.4
8.5
8.6
Internal Memory ............................................................................................................... 133
Block Diagram ........................................................................................................................ 133
Functional Description ............................................................................................................. 133
SRAM Memory ........................................................................................................................ 133
Flash Memory ......................................................................................................................... 134
Flash Memory Initialization and Configuration ........................................................................... 135
Flash Programming ................................................................................................................. 135
Nonvolatile Register Programming ........................................................................................... 136
Register Map .......................................................................................................................... 136
Flash Register Descriptions (Flash Control Offset) ..................................................................... 137
Flash Register Descriptions (System Control Offset) .................................................................. 144
9
9.1
9.1.1
9.1.2
9.1.3
9.1.4
9.1.5
9.1.6
9.2
9.3
9.4
General-Purpose Input/Outputs (GPIOs) ....................................................................... 157
Functional Description ............................................................................................................. 157
Data Control ........................................................................................................................... 157
Interrupt Control ...................................................................................................................... 158
Mode Control .......................................................................................................................... 159
Commit Control ....................................................................................................................... 159
Pad Control ............................................................................................................................. 159
Identification ........................................................................................................................... 160
Initialization and Configuration ................................................................................................. 160
Register Map .......................................................................................................................... 161
Register Descriptions .............................................................................................................. 163
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Preliminary
September 02, 2007
LM3S1138 Microcontroller
10
10.1
10.2
10.2.1
10.2.2
10.2.3
10.3
10.3.1
10.3.2
10.3.3
10.3.4
10.3.5
10.3.6
10.4
10.5
General-Purpose Timers ................................................................................................. 198
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
GPTM Reset Conditions ..........................................................................................................
32-Bit Timer Operating Modes ..................................................................................................
16-Bit Timer Operating Modes ..................................................................................................
Initialization and Configuration .................................................................................................
32-Bit One-Shot/Periodic Timer Mode .......................................................................................
32-Bit Real-Time Clock (RTC) Mode .........................................................................................
16-Bit One-Shot/Periodic Timer Mode .......................................................................................
16-Bit Input Edge Count Mode .................................................................................................
16-Bit Input Edge Timing Mode ................................................................................................
16-Bit PWM Mode ...................................................................................................................
Register Map ..........................................................................................................................
Register Descriptions ..............................................................................................................
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
Initialization and Configuration .................................................................................................
Register Map ..........................................................................................................................
Register Descriptions ..............................................................................................................
199
199
199
199
201
205
205
206
206
207
207
208
208
209
234
234
235
235
236
11
11.1
11.2
11.3
11.4
11.5
Watchdog Timer ............................................................................................................... 234
12
12.1
12.2
12.2.1
12.2.2
12.2.3
12.2.4
12.2.5
12.2.6
12.3
12.3.1
12.3.2
12.4
12.5
Analog-to-Digital Converter (ADC) ................................................................................. 257
Block Diagram ........................................................................................................................ 258
Functional Description ............................................................................................................. 258
Sample Sequencers ................................................................................................................ 258
Module Control ........................................................................................................................ 259
Hardware Sample Averaging Circuit ......................................................................................... 260
Analog-to-Digital Converter ...................................................................................................... 260
Test Modes ............................................................................................................................. 260
Internal Temperature Sensor .................................................................................................... 260
Initialization and Configuration ................................................................................................. 261
Module Initialization ................................................................................................................. 261
Sample Sequencer Configuration ............................................................................................. 261
Register Map .......................................................................................................................... 262
Register Descriptions .............................................................................................................. 263
13
13.1
13.2
13.2.1
13.2.2
13.2.3
13.2.4
13.2.5
13.2.6
13.2.7
13.2.8
13.3
13.4
Universal Asynchronous Receivers/Transmitters (UARTs) ......................................... 290
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
Transmit/Receive Logic ...........................................................................................................
Baud-Rate Generation .............................................................................................................
Data Transmission ..................................................................................................................
Serial IR (SIR) .........................................................................................................................
FIFO Operation .......................................................................................................................
Interrupts ................................................................................................................................
Loopback Operation ................................................................................................................
IrDA SIR block ........................................................................................................................
Initialization and Configuration .................................................................................................
Register Map ..........................................................................................................................
291
291
291
292
293
293
294
294
295
295
295
296
September 02, 2007
Preliminary
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