White Electronic Designs
4Mx64 Synchronous DRAM
FEATURES
High Frequency = 100, 125, 133MHz
Package:
• 219 Plastic Ball Grid Array (PBGA), 21 x 21mm
Single 3.3V ±0.3V power supply
Fully Synchronous; all signals registered on positive
edge of system clock cycle
Internal pipelined operation; column address can be
changed every clock cycle
Internal banks for hiding row access/precharge
Programmable Burst length 1,2,4,8 or full page
4096 refresh cycles
Commercial, Industrial and Military Temperature
Ranges
Organized as 4M x 64
• User Configurable as 2x4Mx32 or 4x4Mx16
Weight: WEDPN4M64V-XBX - 2 grams typical
WEDPN4M64V-XBX
GENERAL DESCRIPTION
The 32MByte (256Mb) SDRAM is a high-speed CMOS,
dynamic random-access ,memory using 4 chips containing
67,108,864 bits. Each chip is internally configured as a
quad-bank DRAM with a synchronous interface. Each of the
chip’s 16,777,216-bit banks is organized as 4,096 rows by
256 columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE
command, which is then followed by a READ or WRITE
command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to
be accessed (BA0, BA1 select the bank; A0-11 select the
row). The address bits registered coincident with the READ
or WRITE command are used to select the starting column
location for the burst access.
The SDRAM provides for programmable READ or WRITE
burst lengths of 1, 2, 4 or 8 locations, or the full page, with
a burst terminate option. An AUTO PRECHARGE function
may be enabled to provide a self-timed row precharge that
is initiated at the end of the burst sequence.
The 256Mb SDRAM uses an internal pipelined architecture to
achieve high-speed operation. This architecture is compatible
with the 2n rule of prefetch architectures, but it also allows
the column address to be changed on every clock cycle to
achieve a high-speed, fully random access. Precharging one
bank while accessing one of the other three banks will hide
the precharge cycles and provide seamless, high-speed,
random-access operation.
The 256Mb SDRAM is designed to operate in 3.3V, low-
power memory systems. An auto refresh mode is provided,
along with a power-saving, power-down mode.
BENEFITS
58% SPACE SAVINGS
Reduced part count
Reduced trace lengths for lower parasitic
capacitance
Laminate interposer for optimum TCE match
Suitable for hi-reliability applications
Upgradeable to 8M x 64 (contact factory for
availability)
*This product is subject to change without notice.
11.9
Discrete Approach
ACTUAL SIZE
21
WEDPN4M64V-XBX
22.3
54
TSOP
54
TSOP
54
TSOP
54
TSOP
21
S
A
V
I
N
G
S
58%
Area
January 2005
Rev. 8
4 x 265mm
2
= 1061mm
2
441mm
2
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
All inputs and outputs are LVTTL compatible. SDRAMs offer
substantial advances in DRAM operating performance,
including the ability to synchronously burst data at a high data
rate with automatic column-address generation, the ability to
interleave between internal banks in order to hide precharge
time and the capability to randomly change column addresses
on each clock cycle during a burst access.
WEDPN4M64V-XBX
REGISTER DEFINITION
MODE REGISTER
The Mode Register is used to define the specific mode
of operation of the SDRAM. This definition includes the
selec-tion of a burst length, a burst type, a CAS latency, an
operating mode and a write burst mode, as shown in Figure
2. The Mode Register is programmed via the LOAD MODE
REGISTER command and will retain the stored information
until it is programmed again or the device loses power.
Mode register bits M0-M2 specify the burst length, M3
specifies the type of burst (sequential or interleaved), M4-M6
specify the CAS latency, M7 and M8 specify the operating
mode, M9 specifies the WRITE burst mode, and M10 and
M11 are reserved for future use.
The Mode Register must be loaded when all banks are
idle, and the controller must wait the specified time before
initiating the subsequent operation. Violating either of these
requirements will result in unspecified operation.
FUNCTIONAL DESCRIPTION
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed (BA0 and BA1 select the bank,
A0-11 select the row). The address bits (A0-7) registered
coincident with the READ or WRITE command are used to
select the starting column location for the burst access.
Prior to normal operation, the SDRAM must be initialized.
The following sections provide detailed information
covering device initialization, register definition, command
descriptions and device operation.
BURST LENGTH
Read and write accesses to the SDRAM are burst oriented,
with the burst length being programmable, as shown
in Figure 2. The burst length determines the maximum
number of column locations that can be accessed for a
given READ or WRITE command. Burst lengths of 1, 2, 4
or 8 locations are available for both the sequential and the
interleaved burst types, and a full-page burst is available
for the sequential type. The full-page burst is used in
conjunction with the BURST TERMINATE command to
generate arbitrary burst lengths.
Reserved states should not be used, as unknown operation
or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of
columns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, meaning
that the burst will wrap within the block if a boundary is
reached. The block is uniquely selected by A1-7 when the
burst length is set to two; by A2-7 when the burst length is set
to four; and by A3-7 when the burst length is set to eight. The
remaining (least significant) address bit(s) is (are) used to
select the starting location within the block. Full-page bursts
wrap within the page if the boundary is reached.
INITIALIZATION
SDRAMs must be powered up and initialized in a predefined
manner. Operational procedures other than those specified
may result in undefined operation. Once power is applied
to V
CC
and V
CCQ
(simultaneously) and the clock is stable
(stable clock is defined as a signal cycling within timing
constraints specified for the clock pin), the SDRAM requires
a 100μs delay prior to issuing any command other than a
COMMAND INHIBIT or a NOP. Starting at some point during
this 100μs period and continuing at least through the end
of this period, COMMAND INHIBIT or NOP commands
should be applied.
Once the 100μs delay has been satisfied with at least
one COMMAND INHIBIT or NOP command having been
applied, a PRECHARGE command should be applied. All
banks must be precharged, thereby placing the device in
the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles must be
performed. After the AUTO REFRESH cycles are complete,
the SDRAM is ready for Mode Register programming. Because
the Mode Register will power up in an unknown state, it should
be loaded prior to applying any operational command.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January 2005
Rev. 8
4
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
FIGURE 2 – MODE REGISTER DEFINITION
A11 A10 A9 A8
A7 A6 A5 A4 A3 A2 A1 A0
WEDPN4M64V-XBX
TABLE 1 – BURST DEFINITION
Burst
Length
2
A1
0
0
1
1
A1
0
0
1
1
0
0
1
1
Starting Column
Address
A0
0
1
A0
0
1
0
1
A0
0
1
0
1
0
1
0
1
Order of Accesses Within a Burst
Type = Sequential
0-1
1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
Cn, Cn + 1, Cn + 2
Cn + 3, Cn + 4...
…Cn - 1,
Cn…
Type = Interleaved
0-1
1-0
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Not Supported
Address Bus
Mode Register (Mx)
Reserved* WB Op Mode CAS Latency
BT
Burst Length
*Should program
M11, M10 = 0, 0
to ensure compatibility
with future devices.
M2 M1M0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
1
2
4
8
Burst Length
M3 = 0
M3 = 1
1
2
4
8
Reserved
Reserved
Reserved
Reserved
4
Reserved
Reserved
Reserved
Full Page
8
M3
0
1
Burst Type
Sequential
Interleaved
A2
0
0
0
0
1
1
1
1
M6 M5 M4
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
CAS Latency
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
Full
Page
(y)
n = A0-9/8/7
(location 0-y)
M8
0
-
M7
0
-
M6-M0
Defined
-
Operating Mode
Standard Operation
All other states reserved
M9
0
1
Write Burst Mode
Programmed Burst Length
Single Location Access
NOTES:
1. For full-page accesses: y = 256.
2. For a burst length of two, A1-7 select the block-of-two burst; A0 selects the starting
column within the block.
3. For a burst length of four, A2-7 select the block-of-four burst; A0-1 select the starting
column within the block.
4. For a burst length of eight, A3-7 select the block-of-eight burst; A0-2 select the
starting column within the block.
5. For a full-page burst, the full row is selected and A0-7 select the starting column.
6. Whenever a boundary of the block is reached within a given sequence above, the
following access wraps within the block.
7. For a burst length of one, A0-7 select the unique column to be accessed, and Mode
Register bit M3 is ignored.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January 2005
Rev. 8
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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