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PLL502-37OC-R

Description
IC,MISCELLANEOUS CLOCK GENERATOR,TSSOP,16PIN,PLASTIC
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size355KB,9 Pages
ManufacturerMicrochip
Websitehttps://www.microchip.com
Environmental Compliance
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PLL502-37OC-R Overview

IC,MISCELLANEOUS CLOCK GENERATOR,TSSOP,16PIN,PLASTIC

PLL502-37OC-R Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerMicrochip
package instructionTSSOP-16
Reach Compliance Codecompli
Other featuresTRI-STATE; ENABLE DISABLE FUNCTION
JESD-30 codeR-PDSO-G16
length5 mm
Number of terminals16
Maximum operating temperature70 °C
Minimum operating temperature
Maximum output clock frequency25 MHz
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP16,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
power supply3/3.3 V
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum slew rate40 mA
Maximum supply voltage3.63 V
Minimum supply voltage2.97 V
Nominal supply voltage3.3 V
surface mountYES
Temperature levelCOMMERCIAL
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
width4.4 mm
uPs/uCs/peripheral integrated circuit typeCLOCK GENERATOR, OTHER
750kHz – 800MHz Low Phase Noise Multiplier VCXO
Universal Low Phase Noise IC’s
FEATURES
Selectable 750kHz to 800MHz range.
Low phase noise output (@ 10kHz frequency off-
set, -142dBc/Hz for 19.44MHz, -125dBc/Hz for
155.52MHz, -115dBc/Hz for 622.08MHz).
LVCMOS (PLL502-37), LVPECL (PLL502-35 and
PLL502-38) or LVDS (PLL502-39) output.
12MHz to 25MHz crystal input.
No external load capacitor or varicap required.
Output Enable selector.
Wide pull range (±200 ppm)
Selectable /16 to x32 frequency divider/multiplier.
3.3V operation.
Available in 16-Pin TSSOP or 16-pin 3x3mm QFN
GREEN/RoHS compliant packages.
PIN CONFIGURATION
(Top View)
VDD
XIN
XOUT
SEL3^
SEL2^
OE
VCON
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SEL0^
SEL1^
GND
CLKC
VDD
CLKT
GND
GND
TSSOP-16L
SEL0^ / VDD*
10
The PLL502-35 (LVPECL with inverted OE), PLL502-
37 (LVCMOS), PLL502-38 (LVPECL), and PLL502-39
(LVDS) are high performance and low phase noise
VCXO IC chips. They provide phase noise perform-
ance as low as –125dBc at 10kHz offset (at 155MHz),
by multiplying the input crystal frequency up to 32x.
The wide pull range (±200 ppm) and very low jitter
make them ideal for a wide range of applications, in-
cluding SONET/SDH and FEC. They accept funda-
mental parallel resonant mode crystals from 12MHz to
25MHz.
VDD / GND*
DESCRIPTION
XOUT
SEL3^
SEL2^
OE
13
14
15
16
12
11
SEL1^
9
XIN
8
7
6
5
GND
CLKC
VDD
CLKT
P502-3x
1
2
3
4
VCON
GND
GND
BLOCK DIAGRAM
SEL[3:0]
OE
VCON
XIN
XOUT
Oscillator
Amplifier
w/
integrated
varicaps
PLL
(Phase
Locked
Loop)
^:
*:
QFN-16L
Internal pull-up
On 3x3 package, PLL502-35/-38 do not have SEL0 available: Pin 10
is VDD, pin 11 is GND. However, PLL502-37/-39 have SEL0 (pin
10), and pin11 is VDD. See pin assignment table for details.
CLKC
CLKT
OUTPUT ENABLE LOGICAL LEVELS
Part #
PLL502-38
OE
0 (Default)
1
0
1 (Default)
State
Output enabled
Tri-state
Tri-state
Output enabled
PLL by-pass
PLL502-3x
PLL502-35
PLL502-37
PLL502-39
OE input: Logical states defined by LVPECL levels for PLL502-38
Logical states defined by LVCMOS levels for PLL502-37/-39
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 9/23/08 Page 1
GND

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