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3D7105: DescriptionMONOLITHIC 5-TAP FIXED DELAY LINE (SERIES 3D7105); File Size31KB，4 Pages; ManufacturerData Delay Devices

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3D7105 Overview

MONOLITHIC 5-TAP FIXED DELAY LINE (SERIES 3D7105)

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3D7105

MONOLITHIC 5-TAP

FIXED DELAY LINE

(SERIES 3D7105)

FEATURES

•

data

delay

devices,

inc.

PACKAGES

N/C

GND

VDD

N/C

1 8

VDD

All-silicon, low-power CMOS

VDD

2 7

technology

3 6

GND

4 5

TTL/CMOS compatible

inputs and outputs

3D7105Z

GND

SOIC

Vapor phase, IR and wave

(150 Mil)

solderable

3D7105M DIP

Auto-insertable (DIP pkg.)

3D7105H Gull-Wing

(300 Mil)

Low ground bounce noise

Leading- and trailing-edge accuracy

VDD

Delay range:

.75 through 80ns

N/C

Delay tolerance:

5% or 1ns

N/C

Temperature stability:

±3%

typical (0C-70C)

N/C

Vdd stability:

±1%

typical (4.75V-5.25V)

N/C

GND

Minimum input pulse width:

30% of total delay

14-pin DIP and 16-pin SOIC available as drop-in

3D7105S SOIC

replacements for hybrid delay lines

(300 Mil)

3D7105 DIP

3D7105G Gull-Wing

3D7105K Unused pins

removed

(300 Mil)

FUNCTIONAL DESCRIPTION

The 3D7105 5-Tap Delay Line product family consists of fixed-delay

CMOS integrated circuits. Each package contains a single delay line,

tapped and buffered at 5 points spaced uniformly in time. Tap-to-tap

(incremental) delay values can range from 0.75ns through 8.0ns. The

input is reproduced at the outputs without inversion, shifted in time as per

the user-specified dash number. The 3D7105 is TTL- and CMOS-

compatible, capable of driving ten 74LS-type loads, and features both

rising- and falling-edge accuracy.

PIN DESCRIPTIONS

VCC

GND

N/C

Delay Line Input

Tap 1 Output (20%)

Tap 2 Output (40%)

Tap 3 Output (60%)

Tap 4 Output (80%)

Tap 5 Output (100%)

+5 Volts

Ground

No Connection

The all-CMOS 3D7105 integrated circuit has been designed as a reliable,

economic alternative to hybrid TTL fixed delay lines. It is offered in a standard 8-pin auto-insertable DIP

and a space saving surface mount 8-pin SOIC.

TABLE 1: PART NUMBER SPECIFICATIONS

PART NUMBER

DIP-8

3D7105M

3D7105H

SOIC-8

3D7105Z

DIP-14

3D7105

3D7105G

3D7105K

SOIC-16

3D7105S

TOLERANCES

TOTAL

DELAY (ns)

TAP-TAP

DELAY

(ns)

Max

Operating

Frequency

INPUT RESTRICTIONS

Absolute

Max

Oper. Freq.

Min

Operating

Pulse Width

Absolute

Min

Oper. P.W.

-.75

41.7 MHz

3.0

1.0*

0.75

0.4

-1

37.0 MHz

4.0

1.0*

1.0

0.5

-1.5

30.3 MHz

6.0

1.0*

1.5

0.7

-2

25.6 MHz

8.0

1.0*

2.0

0.8

-2.5

22.2 MHz

10.0

1.0*

2.5

1.0

-4

15.9 MHz

16.0

1.0*

4.0

1.3

-5

13.3 MHz

25.0

1.3

5.0

1.5

-8

9.52 MHz

40.0

2.0

8.0

1.5

* Total delay referenced to Tap1 output; Input-to-Tap1 = 5.0ns

1.0ns

NOTE: Any dash number between .75 and 8 not shown is also available.

166.7 MHz

133.3 MHz

83.3 MHz

66.7 MHz

41.7 MHz

12.0 ns

13.5 ns

16.5 ns

19.5 ns

22.5 ns

31.5 ns

37.5 ns

52.5 ns

3.00 ns

3.75 ns

6.00 ns

7.50 ns

12.0 ns

1996 Data Delay Devices

Doc #96006

12/2/96

DATA DELAY DEVICES, INC.

3 Mt. Prospect Ave. Clifton, NJ 07013

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