DATA SHEET
MARCH 1999
LXP610
Low-Jitter Multi-Rate Clock Adapter (CLAD)
General Description
The LXP610 Multi-Rate Clock Adapter (CLAD) offers
pin-selectable frequency conversion between T1 and E1
rates as well as 8 additional rates from 1.544 MHz to
8.192 MHz. The output clock is frequency-locked to the
input clock. When an input frame sync pulse is provided,
the CLAD phase-locks the input and output clocks
together, and locks the 8 kHz output frame sync pulse to the
input frame sync pulse. The frame sync polarity is also pin-
selectable.
Five different high frequency output clocks are available
for applications which require a higher-than-baud rate
backplane or system clock. The high frequency output
(HFO) clock varies with the input clock frequency.
Level One’s patented locking method enables the CLAD to
perform frequency conversion with no external
components, while generating very little jitter on the output
clock. The conversion is digitally controlled so the output
clock is as accurate as the input clock.
The CLAD is an advanced CMOS device and requires only
a single +5 V power supply.
Revision 1.1
Features
• Translates between 10 different frequencies.
• Generates basic and high frequency output clocks and
frame sync from an input clock and its frame sync.
• High Frequency Output clock for higher-than-baud
rate backplane systems
• Low output jitter meets AT&T Publication 62411 for
1.544 MHz, and ITU Recommendation G.823 for
2.048 MHz
• Digital control of frequency conversion process
• No external components
• Pin-selectable operation mode
• Low-power 5 V only CMOS in 14-pin plastic DIP, 28-
pin PLCC and 16 pin SOIC packages
Applications
• Internal timing system for Channel Banks, Digital
Loop Carriers, Multiplexers, Internal Timing
Generators, etc.
• Conversion between T1/E1 clock rates and higher
frequency backplane rates (T1/E1 converter)
• Special backplane interfaces (e.g. NTI 2.56 MHz)
LXP610 Block Diagram
CLKI
Input
Divider
Analog
Phase-Locked
Loop
Output
Divider
HFO
CLKO
Feedback
Divider
SEL
FSI
P1
P2
P3
P4
Frequency
Converter
Frame Sync
Generator
FSP
FSO
Frequency
Select
Logic
Refer to www.level1.com for most current information.
LXP610 Low-Jitter Multi-Rate Clock Adapter (CLAD)
PIN ASSIGNMENTS AND SIGNAL DESCRIPTIONS
Figure 1: LXP610 Pin Assignments
P3
FSO
HFO
n/c
CLKI
CLKO
P1
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VCC
P4
FSI
FSP
SEL
P2
GND
LXP610NE
P3
FSO
n/c
HFO
CLKI
n/c
CLKO
P1
2
n/c
CLKO
P1
GND
P2
n/c
n/c
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC
P4
FSI
FSP
SEL
n/c
P2
GND
12
13
14
15
16
17
18
n/c
HFO
n/c
n/c
n/c
CLKI
n/c
4
3
2
1
28
27
26
5
6
7
8
9
10
11
n/c
n/c
FSO
P3
VCC
P4
n/c
LXP610PE
25
24
23
22
21
20
19
n/c
FSI
n/c
FSP
n/c
SEL
n/c
LXP610SE
LXP610 Pin Assignments and Signal Descriptions
Table 1:
Pin Descriptions
Pin #
Sym
DIP
1
7
9
13
2
PLCC
1
14
16
27
2
SOIC
1
8
10
15
2
P3
P1
P2
P4
FSO
DI
DI
DI
DI
DO
Frame Sync Output.
Frame synchronization output pulse at 8 kHz.
FSO is synchronized to CLKO and to FSI (if FSI is provided). Pulse
width is programmable as specified in Table 2. FSO is active Low
when FSP = 0; active High when FSP = 1.
High Frequency Output.
A high frequency output that may be used
to clock external devices. The HFO output frequency is determined by
P1-P4 and SEL pins as specified in Table 2.
Clock Input.
Primary rate clock to be converted.
Clock Output.
Primary rate clock derived from CLKI.
Ground.
Connect to power supply ground
Mode Select.
Controls frequency conversion and FSO pulse width.
Used in conjunction with P1-P4 pins as specified in Table 2.
Frame Sync Polarity.
When High, causes FSI and FSO to be active
High pulses.
Frame Sync Input.
Frame synchronization pulse (8 kHz or any sub-
rate multiple). Active Low when FSP = 0. Active High when FSP = 1.
Power Supply.
+5 V power supply.
Not Connected.
These pins must be left unconnected.
Program Pins.
These signals control frequency conversion and FSO
pulse width as specified in Table 2. Used in conjunction with SEL pin.
I/O
Description
3
6
4
HFO
DO
5
6
8
10
11
12
14
4
10
13
15
20
22
24
28
3, 4, 5,
7, 8, 9,
11, 12,
17, 18,
19, 21,
23, 25,
26
5
7
9
12
13
14
16
3, 6, 11
CLKI
CLKO
GND
SEL
FSP
FSI
VCC
n/c
DI
D0
S
DI
DI
DI
S
–
1. DI = Digital Input; DO = Digital Output; AI = Analog Input; AO = Analog Output; S = Supply.
3
LXP610 Low-Jitter Multi-Rate Clock Adapter (CLAD)
FUNCTIONAL DESCRIPTION
The CLAD converts an input clock (CLKI) at a particular
frequency to an output clock (CLKO) at a different
frequency. It also produces a frame sync output (FSO) and
a high frequency output clock (HFO). The HFO frequency
is a multiple (2x, 3x, 4x, or 5x) of CLKO. The specific
frequencies are determined by the Mode Select (SEL) and
Program (P1 - P4) inputs. Tables 2 and 3 list the CLKO and
HFO frequencies available with a given input CLKI. Table
2 is keyed to Program Pin settings; Table 3 is keyed to
CLKI frequencies. Refer to Test Specifications for output
frame sync alignments.
CLKO is always frequency-locked to CLKI. When a frame
sync input (FSI) is supplied, CLKI and CLKO are also
phase-locked. The CLAD accepts FSI pulses at 8 kHz, or
at any sub-rate multiple (i.e., 1, 2 or 4 kHz). The frame
sync output (FSO) pulse is synchronized to the FSI pulse.
The pulse width of FSO is programmable as shown in
Tables 2 and 3. A long FSO pulse is one CLKO period
wide and centered on the rising edge of CLKO. A short
pulse is one half of the CLKO period wide and centered on
the rising edge of CLKO.
When an 8 kHz FSI is first asserted, the CLKI and CLKO
rising edges will be aligned within a maximum of 500 ms.
For other FSI rates, the alignment period is
correspondingly lengthened. For example, at 4 kHz, the
FSI/FSO alignment is completed within a maximum of one
second.
If an input frame sync pulse is not provided, the FSI pin
should be tied High or Low. CLKO and FSO are still
generated with the CLKO frequency locked to CLKI.
Table 2:
Program Pin Functions
SEL = 0
CLKI
CLKO
(MHz)
SEL = 1
FSO
pulse width
HFO
(MHz)
CLKI
(MHz)
CLKO
(MHz)
HFO
(MHz)
FSO
pulse width
P4 P3 P2 P1
(MHz)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1.544
3.088
1.544
1.544
1.544
6.176
1.544
6.176
3.088
3.088
3.088
1.544
6.176
6.176
6.176
6.176
2.048
2.048
2.048
2.048
2.560
4.096
2.560
2.048
2.048
4.096
2.048
4.096
2.560
4.096
2.560
4.096
6.144
8.192
6.144
8.192
7.680
8.192
7.680
8.192
6.144
8.192
6.144
8.192
7.680
8.192
7.680
8.192
Long
Short
Long
Short
Long
Long
Long
Short
Long
Long
Long
Long
Long
Long
Long
Long
2.048
2.048
2.048
2.048
2.560
8.192
2.560
8.192
2.048
4.096
2.048
4.096
2.560
8.192
2.560
8.192
3.088
3.088
1.544
1.544
1.544
3.088
1.544
1.544
3.088
3.088
3.088
1.544
1.544
3.088
1.544
1.544
6.176
6.176
6.176
6.176
7.720
6.176
7.720
6.176
6.176
6.176
6.176
6.176
7.720
6.176
7.720
6.176
Long
Long
Long
Long
Long
Long
Long
Long
Long
Long
Long
Long
Long
Long
Long
Long
4
LXP610 Functional Description
Output Jitter
The CLAD output jitter meets the following specifications:
• 2.048 MHz or 4.096 MHz to 1.544 MHz: In this
mode of operation, the CLAD meets the output jitter
requirements of AT&T Publication 62411. When
there is no jitter on input clock CLKI, the maximum
jitter on CLKO is 0.020 UI pp with no bandlimiting,
0.010 UI in the 10 Hz - 40 kHz band, and 0.012 UI in
the 8 - 40 kHz band.
• 1.544 MHz to 2.048 MHz or 4.096 MHz: In this mode
of operation, when there is no jitter on input clock
CLKI, the maximum jitter on CLKO is 0.035 UI pp
over the range of 20 Hz to 100 kHz, and 0.025 UP pp
in the 18-100 kHz band.
Jitter Transfer
The CLAD is sensitive to jitter on the input clock in certain
frequency bands. The jitter transfer curve is determined by
the frequency and amplitude of the input jitter. Figures 4
and 5 on page 9 show nominal jitter transfer measured in
nanoseconds. These figures graph output jitter (less
intrinsic jitter) divided by input jitter (0.25 UI). Jitter
transfer from a 2.048 MHz CLKI to a 1.544 MHz CLKO is
shown in Figure 4. In this mode, jitter in the critical 8 kHz
band is attenuated while jitter in the 18 - 70 kHz band is
transferred with a small net gain. Jitter transfer from a
1.544 MHz CLKI to a 2.048 MHz CLKO is shown in
Figure 5. In both modes, with an input jitter level of 0.25
UI, jitter transfer is held below a net gain of 1.110. (Jitter
transfer varies with the input jitter level. Performance in a
particular application should be verified in the actual
circuit.)
Table 3:
CLKI
(MHz)
Input to Output Frequency Conversion Options
CLKO
(MHz)
HFO
(MHz)
FSO
pulse width
Long
Short
Long
Long
Long
Long
Long
Long
Short
Long
Long
Long
Short
Long
Long
Long
Long
P4 P3 P2 P1
0
0
0
1
0
0
1
X
1
0
1
1
1
0
1
0
1
X
X
0
0
1
0
0
0
0
1
0
0
0
0
0
1
1
1
1
1
1
X
1
X
1
1
0
X
X
X
0
0
1
0
1
X
0
X
1
0
0
1
0
1
X
X
0
0
0
1
1
1
1
1
0
1
1
1
1
SEL
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
0
0
1
1
1.544
1.544
1.544
1.544
2.048
2.048
2.048
2.560
3.088
3.088
3.088
4.096
4.096
6.176
6.176
6.176
6.176
8.192
8.192
2.048
2.048
2.560
4.096
1.544
3.088
3.088
1.544
2.048
2.048
4.096
1.544
3.088
2.048
2.560
4.096
4.096
1.544
3.088
6.144
8.192
7.680
8.192
6.176
6.176
6.176
7.720
6.144
8.192
8.192
6.176
6.176
8.192
7.680
8.192
8.192
6.176
6.176
5
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