LXP610NE datasheet, PDF - EEWORLD Datasheet

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LXP610NE: DescriptionTelecom Circuit, 1-Func, CMOS, PDIP14, PLASTIC, DIP-14; CategoryWireless rf/communication Telecom circuit; File Size335KB，16 Pages; ManufacturerIntel; Websitehttp://www.intel.com/

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LXP610NE Overview

Telecom Circuit, 1-Func, CMOS, PDIP14, PLASTIC, DIP-14

LXP610NE Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Parts packaging code	DIP
package instruction	DIP, DIP14,.3
Contacts	14
Reach Compliance Code	compliant
JESD-30 code	R-PDIP-T14
JESD-609 code	e0
length	19.177 mm
Number of functions	1
Number of terminals	14
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP14,.3
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Certification status	Not Qualified
Maximum seat height	5.334 mm
Maximum slew rate	14 mA
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Telecom integrated circuit types	TELECOM CIRCUIT
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.62 mm
Base Number Matches	1

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DATA SHEET

MARCH 1999

LXP610

Low-Jitter Multi-Rate Clock Adapter (CLAD)

General Description

The LXP610 Multi-Rate Clock Adapter (CLAD) offers

pin-selectable frequency conversion between T1 and E1

rates as well as 8 additional rates from 1.544 MHz to

8.192 MHz. The output clock is frequency-locked to the

input clock. When an input frame sync pulse is provided,

the CLAD phase-locks the input and output clocks

together, and locks the 8 kHz output frame sync pulse to the

input frame sync pulse. The frame sync polarity is also pin-

selectable.

Five different high frequency output clocks are available

for applications which require a higher-than-baud rate

backplane or system clock. The high frequency output

(HFO) clock varies with the input clock frequency.

Level One’s patented locking method enables the CLAD to

perform frequency conversion with no external

components, while generating very little jitter on the output

clock. The conversion is digitally controlled so the output

clock is as accurate as the input clock.

The CLAD is an advanced CMOS device and requires only

a single +5 V power supply.

Revision 1.1

Features

• Translates between 10 different frequencies.

• Generates basic and high frequency output clocks and

frame sync from an input clock and its frame sync.

• High Frequency Output clock for higher-than-baud

rate backplane systems

• Low output jitter meets AT&T Publication 62411 for

1.544 MHz, and ITU Recommendation G.823 for

2.048 MHz

• Digital control of frequency conversion process

• No external components

• Pin-selectable operation mode

• Low-power 5 V only CMOS in 14-pin plastic DIP, 28-

pin PLCC and 16 pin SOIC packages

Applications

• Internal timing system for Channel Banks, Digital

Loop Carriers, Multiplexers, Internal Timing

Generators, etc.

• Conversion between T1/E1 clock rates and higher

frequency backplane rates (T1/E1 converter)

• Special backplane interfaces (e.g. NTI 2.56 MHz)

LXP610 Block Diagram

CLKI

Input

Divider

Analog

Phase-Locked

Loop

Output

Divider

HFO

CLKO

Feedback

Divider

SEL

FSI

Frequency

Converter

Frame Sync

Generator

FSP

FSO

Frequency

Select

Logic

Refer to www.level1.com for most current information.

LXP610NE Related Products

	LXP610NE	LXP610PE	LXP610SE
Description	Telecom Circuit, 1-Func, CMOS, PDIP14, PLASTIC, DIP-14	Telecom Circuit, 1-Func, CMOS, PQCC28, PLASTIC, LCC-28	Telecom Circuit, 1-Func, CMOS, PDSO16, SOIC-16
Parts packaging code	DIP	QLCC	SOIC
package instruction	DIP, DIP14,.3	QCCJ, LDCC28,.5SQ	SOP,
Contacts	14	28	16
Reach Compliance Code	compliant	compliant	unknown
JESD-30 code	R-PDIP-T14	S-PQCC-J28	R-PDSO-G16
length	19.177 mm	11.5062 mm	10.3 mm
Number of functions	1	1	1
Number of terminals	14	28	16
Maximum operating temperature	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	DIP	QCCJ	SOP
Package shape	RECTANGULAR	SQUARE	RECTANGULAR
Package form	IN-LINE	CHIP CARRIER	SMALL OUTLINE
Certification status	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	5.334 mm	4.57 mm	2.65 mm
Nominal supply voltage	5 V	5 V	5 V
surface mount	NO	YES	YES
technology	CMOS	CMOS	CMOS
Telecom integrated circuit types	TELECOM CIRCUIT	TELECOM CIRCUIT	TELECOM CIRCUIT
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal form	THROUGH-HOLE	J BEND	GULL WING
Terminal pitch	2.54 mm	1.27 mm	1.27 mm
Terminal location	DUAL	QUAD	DUAL
width	7.62 mm	11.5062 mm	7.5 mm
Base Number Matches	1	1	1
Encapsulate equivalent code	DIP14,.3	LDCC28,.5SQ	-
power supply	5 V	5 V	-
Maximum slew rate	14 mA	14 mA	-

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