EMD12324P-60 datasheet, PDF - EEWORLD Datasheet

Preliminary

EMD12324P

512M: 16M x 32 Mobile DDR SDRAM

Document Title

512M: 16M x 32 Mobile DDR SDRAM

Revision History

Revision No.

0.0

Date

Aug 21, 2007

History

Initial Draft

Emerging Memory & Logic Solutions Inc.

4F Korea Construction Financial Cooperation B/D, 301-1 Yeon-Dong, Jeju-Do, Korea Zip Code : 690-717

Tel : +82-64-740-1700 Fax : +82-64-740-1750 / Homepage : www.emlsi.com

The attached datasheets provided by EMLSI reserve the right to change the specifications and products.

EMLSI will answer to your questions about device. If you have any questions, please contact the EMLSI

office.

1

Rev 0.0

Preliminary

EMD12324P

512M: 16M x 32 Mobile DDR SDRAM

512M : 16M x 32bit Mobile DDR SDRAM

FEATURES

1.8V power supply, 1.8V I/O power

LVCMOS compatible with multiplexed address.

Double-data-rate architecture; two data transfers per clock

cycle

Bidirectional data strobe(DQS)

Four banks operation.

MRS cycle with address key programs.

CAS latency (2, & 3).

Burst length (2, 4, & 8).

Burst type (Sequential & Interleave).

Differential clock inputs(CK and CKB).

EMRS cycle with address key programs.

PASR(Partial Array Self Refresh).

DS (Driver Strength)

Internal auto TCSR

(Temperature Compensated Self Refresh)

Deep power-down(DPD) mode.

DM for write masking only.

Auto refresh and self refresh modes.

64 refresh period (8K cycle).

Operating temperature range (-25 ~ 85 ).

£

¢

¡

GENERAL DESCRIPTION

This EMD12324P is 536,870,912 bits synchronous double data

rate Dynamic RAM. Each 134,217,728 bits bank is organized as

8,192 rows by 512columns by 32 bits, fabricated with EMLSI’s

high performance CMOS technology.

This device uses a double data rate architecture to achieve high-

speed operation. The double data rate architecture is essentially

a 2n-prefetch architecture with an interface designed to transfer

two data words per clock cycle at the I/O balls.

Range of operating frequencies, programmable burst lengths

and programmable latencies allow the same device to be useful

for a variety of high bandwidth and high performance memory

system applications.

Table 1: ORDERING INFORMATION

Part No.

EMD12324P-75(DDR266)

133

NOTE :

1. EMLSI is not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake.

Please contact to the memory marketing team in EMLSI when considering the use of a product contained herein for any specific purpose,

such as medical, aerospace, nuclear, military, vehicular or undersea repeater use.

(CL3), 83

¡

Max Freq.

166

(CL3), 111

(CL2)

Interface

LVCMOS

Package

Wafer Biz.

Remark

EMD12324P-60(DDR332)

2

Rev 0.0

Preliminary

EMD12324P

512M: 16M x 32 Mobile DDR SDRAM

Table 2: Pad Description

Symbol

Type

Descriptions

Clock : CK and CKB are differential clock inputs. All address and control input signals are sampled on

the crossing of the positive edge of CK and negative edge of CKB. Input and output data is referenced

to the crossing of CK and CKB(both directions of crossing). Internal clock signals are derived from CK/

CKB.

Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input

buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF

REFRESH operation(all banks idle), or ACTIVE POWER-DOWN(row ACTIVE in any bank). CKE is

synchronous for all functions except for SELF REFRESH EXIT, which is achieved asynchronously.

Input buffers, excluding CK, CKB and CKE, are disabled during power-down and self refresh mode

which are contrived for low standby power consumption.

Chip Select : CSB enables (registered LOW) and disables (registered HIGH) the command decoder. All

commands are masked when CSB is registered HIGH. CSB provides for external bank selection on

systems with multiple banks. CSB is considered part of the command code.

Command Inputs: CASB, RASB, and WEB(along with CSB) define the command being entered.

Input Data Mask: DM is an input mask signal for write data. Input data is masked when

DM is sampled. HIGH along with that input data during a WRITE access. DM is sampled

on both edges of DQS. Data Mask pins include dummy loading internally, to match the DQ

and DQS loading.

Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRECHARGE

command is being applied.

Address Inputs: provide the row address for ACTIVE commands, and the column address and AUTO

PRECHARGE bit for READ / WRITE commands, to select one location out of the memory array in the

respective bank. The address inputs also provide the op-code during a MODE REGISTER SET com-

mand.

Data Bus: Input / Output

Data Strobe: Output with read data, input with write data. Edge-aligned with read data,

center-aligned with write data. Used to capture write data. For x32 device, DQS0 corresponds

to the data on DQ0-DQ7, DQS1 corresponds to the data on DQ8-DQ15, DQS2 corresponds

to the data on DQ16-DQ23, and DQS3 corresponds to the data on DQ24-DQ31

CK, CKB

Input

CKE

Input

CSB

RASB, CASB,

WEB

Input

DM0~DM3

Input

BA0, BA1

Input

A0 ~ A12

Input

DQ0~DQ31

I/O

DQS0~DQS3

I/O

VDD

Supply Power Supply

3

Rev 0.0

Preliminary

EMD12324P

512M: 16M x 32 Mobile DDR SDRAM

Device Operation

Simplified State Diagram

Power

applied

Power

On

DPDSX

Deep

Power

Down

Precharge

All Banks

DPDS

REFS

Self

Refresh

REFSX

MRS

EMRS

MRS

Idle

All banks

precharged

REFA

Auto

Refresh

CKEL

CKEH

Active

Power

Down

ACT

CKEH

CKEL

Precharge

Power

Down

Row

Active

WRITE

WRITEA

READ

Burst

Stop

BST

READA

READ

WRITE

READ

WRITEA

READA

WRITE A

PRE

READ A

PRE

Precharge

PREALL

Automatic Sequence

Command Sequence

ACT = Active

BST = Burst Terminate

CKEL = Enter Power-Down

CKEH =Exit Power-Down

DPDS = Enter Deep Power-Down

DPDSX = Exit Deep Power-Down

EMRS = Ext. Mode Reg. Set

MRS = Mode Register Set

PRE = Precharge

PREALL = Precharge All Banks

REFA = Auto Refresh

REFS = Enter Self Refresh

REFSX = Exit Self Refresh

READ = Read w/o Auto Precharge

READA = Read with Auto Precharge

WRITE = Write w/o Auto Precharge

WRITEA = Write with Auto Precharge

4

Rev 0.0

Preliminary

EMD12324P

512M: 16M x 32 Mobile DDR SDRAM

FUNCTIONAL BLOCK DIAGRAM

REFRESH

COUNTER

13

BANK

MEMORY

ROW -

ADDRESS

DECODER

8,192

DQS

GENERATOR

4

DQS

DRIVER

4

ARRAY

(8,192 x 256 x 64)

x4

64

Dout

Parallel

to

Serial

32

13

Dout

DRIVER

32

x4

ADDRESS

REGISTER

A0 - A12

BA0, BA1

SENSE AMPLIFIERS

DQ0~

DQ31

¤

256

2

BANK

CONTROL

LOGIC

COLUMN -

ADDRESS

DECODER

64

Din

Serial

to

Parallel

15

32

x4

I/O GATING

DM MASK LOGIC

Din

INPUT BUF.

32

8

1

4

13

¤

WEB

¤

CASB

¤

RASB

¤

CSB

¤

CKB

¤

CK

¤

CKE

CONTROL

LOGIC

COMMAND

DECODE

STANDARD MODE

REGISTER

EXTENDED MODE

REGISTER

5

¤

DM

INPUT BUF.

4

¤

DQS

INPUT BUF.

4

¤

DQS0~

DQS3

DM0~

DM3

Rev 0.0

EMD12324P-60

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