Supply Voltage Range (Typical). . . . . . . . . . . . . . . . . . . 9.0V to 60V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
*An accidental short between VCC5 and GND may cause excessive heating and permanent damage to the device.
NOTES:
1.
θ
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For
θ
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
3. Additional heatsinking may be required to insure that the junction temperature does not exceed above +125°C.
Electrical Specifications
Unless otherwise specified the specifications listed in the table are tested at T
A
= +25°C and guard band for the
full Temperature Range, V
IN
= 48V, V
OUT
= 5.0V, I
OUT
= 0A. Typical values are at T
A
= +25°C. Parameters
with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits
established by characterization and are not production tested.
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
PARAMETER
VIN SUPPLY
Input Voltage Range
VIN SUPPLY CURRENT
Shut-down Current
9.0
24
60
V
IDD
V
IN
= 9V, EN = HIGH
V
IN
= 60V, EN = HIGH
35
60
3.6
6.0
60
110
4
8.0
µA
µA
mA
mA
Operating Current
IDD
V
IN
= 9V, V
FB
= 1.5V
V
IN
= 60V, V
FB
= 1.5V
VCC5 SUPPLY
(A 1µF capacitor is needed from VCC5 to GND)
VCC5 Output Voltage
Maximum Output Current
INPUT UV
Rising UV Threshold
UV Threshold Hysteresis
BUCK CONVERTER
Output Voltage (Note 3)
Maximum Duty Cycle
Minimum Controllable ON Time
OSCILLATOR
Total Variation on Set Frequency
Frequency Range (Set by RTCT)
SYNC Range
Tested Oscillation Frequency
f
OSC
f
OSC
f
OSC
V
IN
= 9V to 60V, R
T
= 100kΩ, C
T
= 1200pF
V
IN
= 9V to 60V, R
T
= 27.4kΩ, C
T
= 220pF
Over the V
IN
range with frequency set by
external resistor and capacitor at RTCT
100
100
60
725
±10
600
600
%
kHz
kHz
kHz
kHz
I
OUT
= 2A
F = 300kHz
F = 300kHz
1.2
90
96
150
V
IN
- 5
V
%
ns
7.8
0.18
0.3
8.9
0.55
V
V
V
IN
= 9.0V to 60V, I
L
= 0mA to 5mA
V
IN
= 24V
4.9
5.0
5.1
5
V
mA
2
FN9244.7
September 19, 2008
ISL8560
Electrical Specifications
Unless otherwise specified the specifications listed in the table are tested at T
A
= +25°C and guard band for the
full Temperature Range, V
IN
= 48V, V
OUT
= 5.0V, I
OUT
= 0A. Typical values are at T
A
= +25°C. Parameters
with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits
established by characterization and are not production tested.
(Continued)
SYMBOL
ΔV
OSC
V
VIN
/ΔV
OSC
V
IN
= 9V
TEST CONDITIONS
MIN
TYP
1
9
150
300
MAX
UNITS
V
P
-
ns
PARAMETER
Max Ramp Amplitude
Modulator Gain
Min OFF Time
REFERENCE AND SOFT-START
Internal Reference Voltage
Soft-Start Current
Soft-Start Threshold
ERROR AMPLIFIER
Transconductance
Gain-Bandwidth Product
Slew Rate
COMP Pin Drive
Internal Feedback Voltage
Internal Feedback Bias Current
OVERCURRENT PROTECTION
Dynamic Current Limit ON Time
Dynamic Current Limit OFF Time
Switch Current Limit
POWER-GOOD (OPEN DRAIN)
Power-Good Lower Threshold
V
REF
I
SS
V
SOFT
8
0.8
1.21
10
12
V
µA
V
g
m
GBW
SR
I
COMP
V
FB
I
FB
T
A
= -40°C to +85°C, V
IN
= 9.0V to 60V
T
A
= -40°C to +85°C, V
FB
= 1.20V
3.9
5.7
15
6
±200
7.2
mS
MHz
V/µs
µA
1.194
1.210
±50
1.222
±100
V
nA
t
OCON
t
OCOFF
I
LIMIT
T
A
= +25°C
3.2
16
4
4.0
4.8
Clock
pulses
SS cycle
A
V
PG-
V
PG+
Fraction of the V
OUT
set point; ~3µs noise filter
Fraction of the V
OUT
set point; ~3µs noise filter
V
PULLUP
= 5.5V
I
PGOOD
= 4mA
85
111
89
115
1
0.5
%
%
µA
V
PGOOD Leakage Current
PGOOD Voltage Low
MOSFET
Switch ON-Resistance
EN
Input HIGH Level (Asserted)
Input LOW Level (Unasserted)
Input Current HIGH
Input Current LOW
SYNC
Input HIGH Level (Asserted)
Input LOW Level (Unasserted)
Input Current HIGH
Input Current LOW
THERMAL SHUT-DOWN
Thermal Shut-down Temperature
Thermal Shut-down Hysteresis
I
PGLKG
r
DS(ON)
I
OUT
= 2A, V
BOOT
= V
IN
+ 5.0V, Tested at wafer
level
0.19
0.355
Ω
VINHIGH
VINLOW
I
ENHIGH
I
ENLOW
V
IN
= 24V
V
IN
= 24V
2.6
1.2
25
25
V
V
µA
µA
VINHIGH
VINLOW
I
SYNCHIGH
I
SYNCLOW
2.6
1.2
0.2
0.2
V
V
µA
µA
Rising Threshold
150
15
°C
°C
3
FN9244.7
September 19, 2008
ISL8560
Pin Descriptions
LX (Pins 1, 2, 15, 16)
There are four output pins that must be connected together
externally in normal operation.
SGND (Pin 8)
The SGND terminal of the ISL8560 provides the return path
for the control and monitor portions of the IC.
FB (Pin 9)
This is the feedback pin. The feedback ratio is set by an
external resistor divider connected to the load.
BOOT (Pin 3)
A capacitor is connected from this pin to the output pin. An
internal 10V supply and an internal Schottky diode provide
the high side voltage to drive the gate of the output DMOS
device.
COMP (Pin 10)
This pin is connected to the output of the Error Amplifier and
is used to compensate the loop. The Error Amplifier is a GM
amplifier.
EN (Pin 4)
The EN input will disable the part and shut-down all function
when it is held high or left OPEN. The EN current will be
10µA typical. An internal pull-up resistor will hold the pin
high. When EN = Low, the part is enabled. Connect to GND
for auto start-up.
REF (Pin 11)
1.20V reference output. Bypass to GND with 0.01µF
capacitor.
PGOOD (Pin 12)
This pin is an open drain output that is turned on when the
feedback voltage is more than ±10% from the reference
voltage, indicating that the output is not within 10% of set
point.
VCC5 (Pin 5)
VCC5 is the +5.0V output pin which provides an output of an
internal supply for supply filtering purposes. A 1µF capacitor
should be connected from this pin to GND. Internal VDD
supply is set at 5.0V (not planned that the user would use
this supply).
PGND (Pin 13)
This pin is used as the ground connection of the power train.
SYNC (Pin 6)
This pin provides a digital input pin to synchronize the
internal oscillator to an external signal. When the sync
function is not used, this pin can be left open or tied to GND.
If the sync function is used, the RTCT timing must be set to a
frequency lower than the sync input frequency. The
termination of the ramp is synchronized with the rising edge
of the sync input signal. There are no duty cycle restrictions
on the input sync signal. Input thresholds are TTL
compatible.
SS (Pin 14)
A capacitor is connected from this pin to GND to determine
the soft-start timing. The soft-start pin internal charging
current is 10µA.
VIN (Pins 17, 18, 19, 20)
The input supply for the PWM regulator power stage.
Connected to DRAIN of the high side MOSFET.
RTCT (Pin 7)
A resistor to VIN and a capacitor to GND determine the
frequency of the saw-tooth oscillator. Resistor range is
R = 20k to 100k. Capacitor range is C = 470pF to 1.2nF. The
oscillator amplitude will vary from approximately 0.9V to 10V
as V
IN
changes from 8.5V to 60V to maintain constant
frequency and provide feed forward. The oscillator will have
a fixed off time, which will establish the maximum on time for
the regulator. This off time will be <200ns. The maximum
duty cycle for a 500kHz system will therefore be
approximately 90% as the frequency of the maximum duty
cycle will increase (95% for 250kHz system). The minimum
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