Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MCF5373DS
Rev. 3, 04/2008
MCF5373
MAPBGA–256
17mm x 17mm
MAPBGA–196
15mm x 15mm
MCF537x ColdFire
®
Microprocessor Data Sheet
Features
• Version 3 ColdFire variable-length RISC processor core
• System debug support
• JTAG support for system level board testing
• On-chip memories
– 16-Kbyte unified write-back cache
– 32-Kbyte dual-ported SRAM on CPU internal bus,
accessible by core and non-core bus masters (e.g., DMA,
FEC, and USB host and OTG)
• Power management
• Embedded Voice-over-IP (VoIP) system solution
• SDR/DDR SDRAM Controller
• Universal Serial Bus (USB) Host Controller
• Universal Serial Bus (USB) On-the-Go (OTG) controller
• Synchronous Serial Interface (SSI)
• Fast Ethernet Controller (FEC)
• Cryptography Hardware Accelerators
• Three Universal Asynchronous Receiver Transmitters
(UARTs)
• I
2
C Module
• Queued Serial Peripheral Interface (QSPI)
• Pulse Width Modulation (PWM) module
• Real Time Clock
• Four 32-bit DMA Timers
• Software Watchdog Timer
• Four Periodic Interrupt Timers (PITs)
• Phase Locked Loop (PLL)
• Interrupt Controllers (x2)
• DMA Controller
• FlexBus (External Interface)
• Chip Configuration Module (CCM)
• Reset Controller
• General Purpose I/O interface
QFP–160
28mm x 28mm
© Freescale Semiconductor, Inc., 2008. All rights reserved.
Table of Contents
1
2
3
MCF537x Family Comparison . . . . . . . . . . . . . . . . . . . . . . . . .3
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . . .4
3.1 PLL Power Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
3.2 USB Power Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
3.3 Supply Voltage Sequencing and Separation Cautions . .5
3.3.1 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . .5
3.3.2 Power Down Sequence . . . . . . . . . . . . . . . . . . . .5
Pin Assignments and Reset States . . . . . . . . . . . . . . . . . . . . .5
4.1 Signal Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
4.2 Pinout—196 MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . .11
4.3 Pinout—160 QFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
5.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
5.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .14
5.3 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
5.4 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . .15
5.5 Oscillator and PLL Electrical Characteristics . . . . . . . .16
5.6 External Interface Timing Characteristics . . . . . . . . . . .17
5.6.1 FlexBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
5.7 SDRAM Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
5.7.1 SDR SDRAM AC Timing Characteristics . . . . .
5.7.2 DDR SDRAM AC Timing Characteristics . . . . .
5.8 General Purpose I/O Timing . . . . . . . . . . . . . . . . . . . .
5.9 Reset and Configuration Override Timing . . . . . . . . . .
5.10 USB On-The-Go . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.11 SSI Timing Specifications . . . . . . . . . . . . . . . . . . . . . .
5.12 I
2
C Input/Output Timing Specifications . . . . . . . . . . . .
5.13 Fast Ethernet AC Timing Specifications . . . . . . . . . . .
5.13.1 MII Receive Signal Timing . . . . . . . . . . . . . . . .
5.13.2 MII Transmit Signal Timing . . . . . . . . . . . . . . . .
5.13.3 MII Async Inputs Signal Timing . . . . . . . . . . . .
5.13.4 MII Serial Management Channel Timing . . . . .
5.14 32-Bit Timer Module Timing Specifications . . . . . . . . .
5.15 QSPI Electrical Specifications . . . . . . . . . . . . . . . . . . .
5.16 JTAG and Boundary Scan Timing . . . . . . . . . . . . . . . .
5.17 Debug AC Timing Specifications . . . . . . . . . . . . . . . . .
Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1 Package Dimensions—196 MAPBGA . . . . . . . . . . . . .
7.2 Package Dimensions—160 QFP . . . . . . . . . . . . . . . . .
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20
22
25
26
27
27
28
30
30
30
31
31
32
32
33
35
35
38
39
40
42
4
5
6
7
8
MCF537x ColdFire
®
Microprocessor Data Sheet, Rev. 3
2
Freescale Semiconductor
MCF537x Family Comparison
1
MCF537x Family Comparison
Table 1. MCF537x Family Configurations
Module
ColdFire Version 3 Core with EMAC
(Enhanced Multiply-Accumulate Unit)
Core (System) Clock
Peripheral and External Bus Clock
(Core clock
÷
3)
Performance (Dhrystone/2.1 MIPS)
Instruction/Data Cache
Static RAM (SRAM)
SDR/DDR SDRAM Controller
USB 2.0 Host
USB 2.0 On-the-Go
Synchronous Serial Interface (SSI)
Fast Ethernet Controller (FEC)
Cryptography Hardware Accelerators
Embedded Voice-over-IP System Solution
UARTs
I
2
C
QSPI
PWM Module
Real Time Clock
32-bit DMA Timers
Watchdog Timer (WDT)
Periodic Interrupt Timers (PIT)
Edge Port Module (EPORT)
Interrupt Controllers (INTC)
16-channel Direct Memory Access (DMA)
FlexBus External Interface
General Purpose I/O (GPIO)
JTAG - IEEE
®
1149.1 Test Access Port
Package
•
—
—
•
•
—
—
3
•
•
—
•
4
•
4
•
2
•
•
up to 46
•
160
QFP
•
•
•
•
•
—
—
3
•
•
•
•
4
•
4
•
2
•
•
up to 62
•
196
MAPBGA
MCF5372 MCF5372L MCF53721 MCF5373 MCF5373L
•
up to
180 MHz
up to
60 MHz
up to 158
•
•
•
up to
180 MHz
up to
60 MHz
up to 158
•
up to
240 MHz
up to
80 MHz
up to 211
The following table compares the various device derivatives available within the MCF537x family.
up to 240 MHz
up to 80 MHz
up to 211
16 Kbytes
32 Kbytes
•
•
•
•
•
—
•
3
•
•
•
•
4
•
4
•
2
•
•
up to 62
•
196
MAPBGA
•
—
—
•
•
•
—
3
•
•
—
•
4
•
4
•
2
•
•
up to 46
•
160
QFP
•
•
•
•
•
•
—
3
•
•
•
•
4
•
4
•
2
•
•
up to 62
•
196
MAPBGA
MCF537x ColdFire
®
Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
3
Ordering Information
2
Ordering Information
Table 2. Orderable Part Numbers
Freescale Part
Number
MCF5372CAB180
MCF5372LCVM240
MCF53721CVM240
MCF5373CAB180
MCF5373LCVM240
Description
MCF5372 RISC Microprocessor
MCF5372 RISC Microprocessor
MCF53721 RISC Microprocessor
MCF5373 RISC Microprocessor
MCF5373 RISC Microprocessor
Package
160 QFP
196 MAPBGA
196 MAPBGA
160 QFP
196 MAPBGA
Speed
180 MHz
240 MHz
240 MHz
180 MHz
240 MHz
Temperature
–40
°
to +85
°
C
–40
°
to +85
°
C
–40
°
to +85
°
C
–40
°
to +85
°
C
–40
°
to +85
°
C
3
3.1
Hardware Design Considerations
PLL Power Filtering
To further enhance noise isolation, an external filter is strongly recommended for PLL analog V
DD
pins. The filter shown in
Figure 1
should be connected between the board V
DD
and the PLLV
DD
pins. The resistor and capacitors should be placed as
close to the dedicated PLLV
DD
pin as possible.
10
Ω
Board IV
DD
10 µF
0.1 µF
PLL V
DD
Pin
GND
Figure 1. System PLL V
DD
Power Filter
3.2
USB Power Filtering
To minimize noise, external filters are required for each of the USB power pins. The filter shown in
Figure 2
should be
connected between the board EV
DD
or IV
DD
and each of the USBV
DD
pins. The resistor and capacitors should be placed as
close to the dedicated USBV
DD
pin as possible.
0
Ω
Board EV
DD
10 µF
0.1 µF
USB V
DD
Pin
GND
Figure 2. USB V
DD
Power Filter
MCF537x ColdFire
®
Microprocessor Data Sheet, Rev. 3
4
Freescale Semiconductor
Pin Assignments and Reset States
NOTE
In addition to the above filter circuitry, a 0.01 F capacitor is also recommended in parallel
with those shown.
3.3
Supply Voltage Sequencing and Separation Cautions
The relationship between SDV
DD
and EV
DD
is non-critical during power-up and power-down sequences. SDV
DD
(2.5V or
3.3V) and EV
DD
are specified relative to IV
DD
.
3.3.1
Power Up Sequence
If EV
DD
/SDV
DD
are powered up with IV
DD
at 0 V, the sense circuits in the I/O pads cause all pad output drivers connected to
the EV
DD
/SDV
DD
to be in a high impedance state. There is no limit on how long after EV
DD
/SDV
DD
powers up before IV
DD
must powered up. IV
DD
should not lead the EV
DD
, SDV
DD
, or PLLV
DD
by more than 0.4 V during power ramp-up or there is
high current in the internal ESD protection diodes. The rise times on the power supplies should be slower than 500 us to avoid
turning on the internal ESD protection clamp diodes.
3.3.2
Power Down Sequence
If IV
DD
/PLLV
DD
are powered down first, sense circuits in the I/O pads cause all output drivers to be in a high impedance state.
There is no limit on how long after IV
DD
and PLLV
DD
power down before EV
DD
or SDV
DD
must power down. IV
DD
should
not lag EV
DD
, SDV
DD
, or PLLV
DD
going low by more than 0.4 V during power down or there is undesired high current in the
ESD protection diodes. There are no requirements for the fall times of the power supplies.
The recommended power down sequence is as follows:
1.
2.
Drop IV
DD
/PLLV
DD
to 0 V.
Drop EV
DD
/SDV
DD
supplies.
4
4.1
Pin Assignments and Reset States
Signal Multiplexing
The following table lists all the MCF537x pins grouped by function. The Dir column is the direction for the primary function
of the pin only. Refer to
Section 7, “Package Information,”
for package diagrams. For a more detailed discussion of the
MCF537x signals, consult the
MCF5373 Reference Manual
(MCF5373RM).
NOTE
In this table and throughout this document, a single signal within a group is designated
without square brackets (i.e., A23), while designations for multiple signals within a group
use brackets (i.e., A[23:21]) and is meant to include all signals within the two bracketed
numbers when these numbers are separated by a colon.
NOTE
The primary functionality of a pin is not necessarily its default functionality. Pins that are
muxed with GPIO default to their GPIO functionality.
MCF537x ColdFire
®
Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
5
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