HN58C1001 Series
1M EEPROM (128-kword
×
8-bit)
Ready/Busy and
RES
function
REJ03C0145-0800Z
(Previous ADE-203-028G (Z) Rev.7.0)
Rev. 8.00
Nov. 27. 2003
Description
Renesas Technology
's
HN58C1001 is an electrically erasable and programmable ROM organized as 131072-
word
×
8-bit. It has realized high speed, low power consumption and high reliability by employing advanced
MNOS memory technology and CMOS process and circuitry technology. It also has a 128-byte page
programming function to make the write operations faster.
Features
•
Single supply: 5.0 V
±
10%
•
Access time: 150 ns (max)
•
Power dissipation
Active: 20 mW/MHz, (typ)
Standby: 110
µW
(max)
•
On-chip latches: address, data,
CE, OE, WE
•
Automatic byte write: 10 ms (max)
•
Automatic page write (128 bytes): 10 ms (max)
•
Data
polling and RDY/Busy
•
Data protection circuit on power on/off
•
Conforms to JEDEC byte-wide standard
•
Reliable CMOS with MNOS cell technology
•
10 erase/write cycles (in page mode)
4
•
10 years data retention
•
Software data protection
•
Write protection by
RES
pin
•
There are also lead free products.
Rev.8.00, Nov. 27.2003, page 1 of 21
HN58C1001 Series
Ordering Information
Type No.
HN58C1001FP-15
HN58C1001T-15
HN58C1001FP-15E
HN58C1001T-15E
Access time
150 ns
150 ns
150 ns
150 ns
Package
525 mil 32-pin plastic SOP (FP-32D)
32-pin plastic TSOP (TFP-32DA)
525 mil 32-pin plastic SOP (FP-32DV)
Lead free
32-pin plastic TSOP (TFP-32DAV)
Lead free
Pin Arrangement
HN58C1001FP Series
RDY/
Busy
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
(Top view)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A15
HN58C1001T Series
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
(Top view)
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A4
A5
A6
A7
A12
A14
A16
RDY/
Busy
V
CC
A15
RES
WE
A3
A2
A1
A13
A0
I/O0
A8
I/O1
A9
I/O2
A11 V
SS
OE
I/O3
A10 I/O4
I/O5
CE
I/O6
I/O7 I/O7
I/O6
CE
A10
I/O5
OE
I/O4
I/O3
RES
WE
A13
A8
A9
A11
Rev.8.00, Nov. 27.2003, page 2 of 21
HN58C1001 Series
Pin Description
Pin name
A0 to A16
I/O0 to I/O7
OE
CE
WE
V
CC
V
SS
RDY/Busy
RES
Function
Address input
Data input/output
Output enable
Chip enable
Write enable
Power supply
Ground
Ready busy
Reset
Block Diagram
I/O0
to
I/O7
High voltage generator
RDY/
Busy
V
CC
V
SS
RES
OE
CE
WE
RES
A0
to
I/O buffer
and
input latch
Control logic and timing
Y decoder
Y gating
A6
Address
buffer and
latch
A7
to
X decoder
Memory array
A16
Data latch
Rev.8.00, Nov. 27.2003, page 3 of 21
HN58C1001 Series
Operation Table
Operation
Read
Standby
Write
Deselect
Write Inhibit
Data
Polling
Program reset
CE
V
IL
V
IH
V
IL
V
IL
×
×
V
IL
×
OE
V
IL
×*
2
WE
V
IH
×
V
IL
V
IH
V
IH
×
V
IH
×
RES
V
H
*
×
V
H
V
H
×
×
V
H
V
IL
1
RDY/Busy
Busy
High-Z
High-Z
High-Z to V
OL
High-Z
V
OL
High-Z
I/O
Dout
High-Z
Din
High-Z
Dout (I/O7)
High-Z
V
IH
V
IH
×
V
IL
V
IL
×
Notes: 1. Refer to the recommended DC operating conditions.
2.
×
: Don’t care
Absolute Maximum Ratings
Parameter
Supply voltage relative to V
SS
Input voltage relative to V
SS
Operating temperature range*
2
Symbol
V
CC
Vin
Topr
Value
−0.6
to +7.0
−0.5*
to +7.0
1
Unit
V
V
°C
0 to +70
Storage temperature range
Tstg
−55
to +125
°C
Notes: 1. Vin min =
−3.0
V for pulse width
≤
50 ns
2. Including electrical characteristics and data retention
Recommended DC Operating Conditions
Parameter
Supply voltage
Symbol
V
CC
V
SS
Input voltage
V
IL
V
IH
V
H
Operating temperature
Note:
Topr
1. V
IL
(min):
−1.0
V for pulse width
≤
50 ns
Min
4.5
0
−0.3*
2.2
V
CC
– 0.5
0
1
Typ
5.0
0
Max
5.5
0
0.8
V
CC
+ 0.3
V
CC
+ 1.0
+70
Unit
V
V
V
V
V
°C
Rev.8.00, Nov. 27.2003, page 4 of 21
HN58C1001 Series
DC Characteristics
(Ta = 0 to +70°C, V
CC
= 5.0V ± 10%)
Parameter
Input leakage current
Output leakage current
Standby V
CC
current
Operating V
CC
current
Symbol
I
LI
I
LO
I
CC1
I
CC2
I
CC3
Min
Output low voltage
Output high voltage
V
OL
V
OH
2.4
Typ
Max
2*
2
20
1
15
50
0.4
1
Unit
µA
µA
µA
mA
mA
mA
V
V
Test conditions
V
CC
= 5.5 V, Vin =5.5 V
V
CC
= 5.5 V, Vout = 5.5/0.4 V
CE
= V
CC
CE
= V
IH
Iout = 0 mA, Duty = 100%,
Cycle = 1 µs, V
CC
= 5.5 V
Iout = 0 mA, Duty = 100%,
Cycle = 150 ns, V
CC
= 5.5 V
I
OL
= 2.1 mA
I
OH
= –400
µA
Notes: 1. I
LI
on
RES:
100
µA
(max)
Capacitance
(Ta = +25°C, f = 1 MHz)
Parameter
Input capacitance*
Note:
1
1
Symbol
Cin
Cout
Min
Typ
Max
6
12
Unit
pF
pF
Test conditions
Vin = 0 V
Vout = 0 V
Output capacitance*
1. This parameter is periodically sampled and not 100% tested.
Rev.8.00, Nov. 27.2003, page 5 of 21
Embedded System
京公网安备 11010802033920号
EEWORLD
