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HD74HC113FPEL

Description
Dual J-K Flip-Flops (with Preset)
Categorylogic    logic   
File Size184KB,7 Pages
ManufacturerRenesas Electronics Corporation
Websitehttps://www.renesas.com/
Environmental Compliance
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HD74HC113FPEL Overview

Dual J-K Flip-Flops (with Preset)

HD74HC113FPEL Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerRenesas Electronics Corporation
Parts packaging codeSOIC
package instructionSOP,
Contacts14
Reach Compliance Codecompli
ECCN codeEAR99
seriesHC/UH
JESD-30 codeR-PDSO-G14
length10.06 mm
Logic integrated circuit typeJ-K FLIP-FLOP
Number of digits2
Number of functions2
Number of terminals14
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output polarityCOMPLEMENTARY
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE
propagation delay (tpd)190 ns
Certification statusNot Qualified
Maximum seat height2.2 mm
Maximum supply voltage (Vsup)6 V
Minimum supply voltage (Vsup)2 V
Nominal supply voltage (Vsup)4.5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Trigger typeNEGATIVE EDGE
width5.5 mm
HD74HC113
Dual J-K Flip-Flops (with Preset)
REJ03D0563-0200
(Previous ADE-205-436)
Rev.2.00
Oct 11, 2005
Description
This flip-flop is edge sensitive to the clock input and change state on the negative going transition of the clock pulse.
Each one has independent J, K, clock, and preset inputs and Q and
Q
inputs. Preset is independent of the clock and
accomplished by a low level on the input.
Features
High Speed Operation: t
pd
(Clock to Q) = 18 ns typ (C
L
= 50 pF)
High Output Current: Fanout of 10 LSTTL Loads
Wide Operating Voltage: V
CC
= 2 to 6 V
Low Input Current: 1
µA
max
Low Quiescent Supply Current: I
CC
(static) = 2
µA
max (Ta = 25°C)
Ordering Information
Part Name
HD74HC113P
HD74HC113FPEL
Package Type
DILP-14 pin
SOP-14 pin (JEITA)
Package Code
(Previous Code)
PRDP0014AB-B
(DP-14AV)
Package
Abbreviation
P
EL (2,000 pcs/reel)
Taping Abbreviation
(Quantity)
PRSP0014DF-B
FP
(FP-14DAV)
Note: Please consult the sales office for the above package availability.
Function Table
Inputs
Preset
L
H
H
H
H
H
H
H
H:
L:
X:
High level
Low level
Irrelevant
H
L
Clock
X
J
X
L
L
H
H
X
X
X
K
X
L
H
L
H
X
X
X
Q
H
No change
L
H
Toggle
No change
No change
No change
H
L
Output
Q
L
Rev.2.00, Oct 11, 2005 page 1 of 6

HD74HC113FPEL Related Products

HD74HC113FPEL HD74HC113 HD74HC113P
Description Dual J-K Flip-Flops (with Preset) Dual J-K Flip-Flops (with Preset) Dual J-K Flip-Flops (with Preset)
Maker Renesas Electronics Corporation - Renesas Electronics Corporation
Parts packaging code SOIC - DIP
package instruction SOP, - 6.30 X 19.20 MM, 2.54 MM PITCH, PLASTIC, DIP-14
Contacts 14 - 14
Reach Compliance Code compli - unknow
ECCN code EAR99 - EAR99
series HC/UH - HC/UH
JESD-30 code R-PDSO-G14 - R-PDIP-T14
length 10.06 mm - 19.2 mm
Logic integrated circuit type J-K FLIP-FLOP - J-K FLIP-FLOP
Number of digits 2 - 2
Number of functions 2 - 2
Number of terminals 14 - 14
Maximum operating temperature 85 °C - 85 °C
Minimum operating temperature -40 °C - -40 °C
Output polarity COMPLEMENTARY - COMPLEMENTARY
Package body material PLASTIC/EPOXY - PLASTIC/EPOXY
encapsulated code SOP - DIP
Package shape RECTANGULAR - RECTANGULAR
Package form SMALL OUTLINE - IN-LINE
propagation delay (tpd) 190 ns - 190 ns
Certification status Not Qualified - Not Qualified
Maximum seat height 2.2 mm - 5.06 mm
Maximum supply voltage (Vsup) 6 V - 6 V
Minimum supply voltage (Vsup) 2 V - 2 V
Nominal supply voltage (Vsup) 4.5 V - 4.5 V
surface mount YES - NO
technology CMOS - CMOS
Temperature level INDUSTRIAL - INDUSTRIAL
Terminal form GULL WING - THROUGH-HOLE
Terminal pitch 1.27 mm - 2.54 mm
Terminal location DUAL - DUAL
Trigger type NEGATIVE EDGE - NEGATIVE EDGE
width 5.5 mm - 7.62 mm

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