HD74ACT165P datasheet, PDF - EEWORLD Datasheet

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HD74ACT165P: DescriptionParallel In Serial Out, ACT Series, 8-Bit, Right Direction, Complementary Output, CMOS, PDIP16, DP-16; Categorylogic logic; File Size68KB，11 Pages; ManufacturerHitachi （Renesas ）; Websitehttp://www.renesas.com/eng/

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HD74ACT165P Overview

Parallel In Serial Out, ACT Series, 8-Bit, Right Direction, Complementary Output, CMOS, PDIP16, DP-16

HD74ACT165P Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Parts packaging code	DIP
package instruction	DIP, DIP16,.3
Contacts	16
Reach Compliance Code	unknown
Other features	CLOCK INHIBIT
Counting direction	RIGHT
series	ACT
JESD-30 code	R-PDIP-T16
JESD-609 code	e0
length	19.2 mm
Logic integrated circuit type	PARALLEL IN SERIAL OUT
Maximum Frequency@Nom-Sup	60000000 Hz
Number of digits	8
Number of functions	1
Number of terminals	16
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output polarity	COMPLEMENTARY
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP16,.3
Package shape	RECTANGULAR
Package form	IN-LINE
propagation delay (tpd)	16.5 ns
Certification status	Not Qualified
Maximum seat height	5.06 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Trigger type	POSITIVE EDGE
width	7.62 mm
minfmax	60 MHz
Base Number Matches	1

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HD74AC165/HD74ACT165

Parallel-Load 8-bit Shift Register

ADE-205-374 (Z)

1st. Edition

Sep. 2000

Description

This 8-bit serial shift register shifts data from Q

to Q

when clocked, Parallel inputs to each stage are

enabled by a low level at the Shift/Load Input. Also included is a gated clock input and a complementary

output from the eighth bit.

Clocking is accomplished through a 2-input NOR gate permitting one input to be used as a clock inhibit

function. Holding either of the clock inputs high inhibits clocking, and holding either clock input low with

the Shift/Load input high enables the other clock input. Data transfer occurs on the positive going edge of

the clock. Parallel loading is inhibited as long as the Shift/Load input is high. When taken low, data at the

parallel inputs is loaded directly into the register independent of the state of the clock.

Features

•

Outputs Source/Sink 24 mA

•

HD74ACT165 has TTL-Compatible Inputs

HD74ACT165P Related Products

	HD74ACT165P	HD74AC165T	HD74AC165FP	HD74AC165P	HD74ACT165RP	HD74AC165RP	HD74ACT165FP
Description	Parallel In Serial Out, ACT Series, 8-Bit, Right Direction, Complementary Output, CMOS, PDIP16, DP-16	Parallel In Serial Out, AC Series, 8-Bit, Right Direction, Complementary Output, CMOS, PDSO16, TTP-16DA	Parallel In Serial Out, AC Series, 8-Bit, Right Direction, Complementary Output, CMOS, PDSO16, FP-16DA	Parallel In Serial Out, AC Series, 8-Bit, Right Direction, Complementary Output, CMOS, PDIP16, DP-16	Parallel In Serial Out, ACT Series, 8-Bit, Right Direction, Complementary Output, CMOS, PDSO16, FP-16DN	Parallel In Serial Out, AC Series, 8-Bit, Right Direction, Complementary Output, CMOS, PDSO16, FP-16DN	Parallel In Serial Out, ACT Series, 8-Bit, Right Direction, Complementary Output, CMOS, PDSO16, FP-16DA
Parts packaging code	DIP	SOIC	SOIC	DIP	SOIC	SOIC	SOIC
package instruction	DIP, DIP16,.3	TSSOP,	SOP, SOP16,.4	DIP, DIP16,.3	SOP,	SOP,	SOP, SOP16,.4
Contacts	16	16	16	16	16	16	16
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown
Other features	CLOCK INHIBIT	ALSO OPRATES AT 5V VCC NOMINAL; CLOCK INHIBIT	ALSO OPRATES AT 5V VCC NOMINAL; CLOCK INHIBIT	ALSO OPRATES AT 5V VCC NOMINAL; CLOCK INHIBIT	CLOCK INHIBIT	ALSO OPRATES AT 5V VCC NOMINAL; CLOCK INHIBIT	CLOCK INHIBIT
Counting direction	RIGHT	RIGHT	RIGHT	RIGHT	RIGHT	RIGHT	RIGHT
series	ACT	AC	AC	AC	ACT	AC	ACT
JESD-30 code	R-PDIP-T16	R-PDSO-G16	R-PDSO-G16	R-PDIP-T16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16
length	19.2 mm	5 mm	10.06 mm	19.2 mm	9.9 mm	9.9 mm	10.06 mm
Logic integrated circuit type	PARALLEL IN SERIAL OUT	PARALLEL IN SERIAL OUT	PARALLEL IN SERIAL OUT	PARALLEL IN SERIAL OUT	PARALLEL IN SERIAL OUT	PARALLEL IN SERIAL OUT	PARALLEL IN SERIAL OUT
Number of digits	8	8	8	8	8	8	8
Number of functions	1	1	1	1	1	1	1
Number of terminals	16	16	16	16	16	16	16
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
Output polarity	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	DIP	TSSOP	SOP	DIP	SOP	SOP	SOP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	IN-LINE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE	IN-LINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE
propagation delay (tpd)	16.5 ns	21.5 ns	21.5 ns	21.5 ns	16.5 ns	21.5 ns	16.5 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	5.06 mm	1.1 mm	2.2 mm	5.06 mm	1.75 mm	1.75 mm	2.2 mm
Maximum supply voltage (Vsup)	5.5 V	3.6 V	3.6 V	3.6 V	5.5 V	3.6 V	5.5 V
Minimum supply voltage (Vsup)	4.5 V	3 V	3 V	3 V	4.5 V	3 V	4.5 V
Nominal supply voltage (Vsup)	5 V	3.3 V	3.3 V	3.3 V	5 V	3.3 V	5 V
surface mount	NO	YES	YES	NO	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal form	THROUGH-HOLE	GULL WING	GULL WING	THROUGH-HOLE	GULL WING	GULL WING	GULL WING
Terminal pitch	2.54 mm	0.65 mm	1.27 mm	2.54 mm	1.27 mm	1.27 mm	1.27 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
Trigger type	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE
width	7.62 mm	4.4 mm	5.5 mm	7.62 mm	3.95 mm	3.95 mm	5.5 mm
minfmax	60 MHz	90 MHz	90 MHz	90 MHz	60 MHz	90 MHz	60 MHz
Is it Rohs certified?	incompatible	-	incompatible	incompatible	-	-	incompatible
JESD-609 code	e0	-	e0	e0	-	-	e0
Maximum Frequency@Nom-Sup	60000000 Hz	-	70000000 Hz	70000000 Hz	-	-	60000000 Hz
Encapsulate equivalent code	DIP16,.3	-	SOP16,.4	DIP16,.3	-	-	SOP16,.4
Terminal surface	Tin/Lead (Sn/Pb)	-	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	-	-	Tin/Lead (Sn/Pb)
Base Number Matches	1	1	1	1	1	-	-
Maker	-	Hitachi （Renesas ）	Hitachi （Renesas ）	Hitachi （Renesas ）	-	Hitachi （Renesas ）	Hitachi （Renesas ）

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