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CPPV7T-B6-01.0000

Description
LVDS Output Clock Oscillator, 1MHz Nom, ROHS COMPLIANT, CERAMIC PACKAGE-6
CategoryPassive components    oscillator   
File Size719KB,1 Pages
ManufacturerCardinal Components
Environmental Compliance  
Download Datasheet Parametric View All

CPPV7T-B6-01.0000 Overview

LVDS Output Clock Oscillator, 1MHz Nom, ROHS COMPLIANT, CERAMIC PACKAGE-6

CPPV7T-B6-01.0000 Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
Reach Compliance Codecompliant
Other featuresENABLE/DISABLE FUNCTION; TUBE
maximum descent time1 ns
Frequency Adjustment - MechanicalNO
frequency stability100%
JESD-609 codee4
Installation featuresSURFACE MOUNT
Nominal operating frequency1 MHz
Maximum operating temperature70 °C
Minimum operating temperature
Oscillator typeLVDS
physical size7.0mm x 5.0mm x 1.8mm
longest rise time1 ns
Maximum supply voltage3.465 V
Minimum supply voltage3.125 V
Nominal supply voltage3.3 V
surface mountYES
maximum symmetry55/45 %
Terminal surfaceGold (Au) - with Nickel (Ni) barrier
Base Number Matches1
Programmable LVDS Oscillator
* LVDS Output
* Field Programmable
* Industry Standard Packaging
CARDINAL
COMPONENTS
CARDINAL
COMPONENTS
Applications
* Serial Communications
* Routers
* Switches
* WAN Interfaces
* Test Equipment
Series
CPPV7
Part Numbering Example:
CPPV7Z-A7BR-Freq.
CPP
V
7
Z
A7
BR
XX.XXXX
SERIES OUTPUT
CPP
V= LVDS
PACKAGE STYLE ADDED FEATURES
OPERATING TEMP.
FREQUENCY
STABILITY
+ 100 ppm 1 ~ 200 MHz
7 = 5X7 Ceramic Blank = Bulk
Blank = - 0°C + 70°C B
6
=
T = Tube
A5 = - 20°C + 70°C BP = + 50 ppm
Z = Tape and Reel A7 = - 40°C + 85°C BR = + 25 ppm
Specifications:
Frequency Range:
Stability:
Supply Voltage:
Operating Temperature:
Storage Temperature:
Duty Cycle:
Start-Up Time:
Aging: (ppm/1st Year)
Ta=25C, Vdd=3.3V
Static Discharge Voltage:
Supply Current:
Short Circuit Current:
Jitter (RMS) Period:
Output Voltage
Voh
Vol
Rise/Fall Time:
Output Level:
Packaging:
2000
40
± 50
6
10
1.6
0.9
0.7
LVDS
Tape and Reel 1000 pcs per Reel
1.0
50
5
ppm
V
mA
mA
pS
V
V
nS
Min
1
-25
3.125
-40
-55
45
3
3.3
Typ
Max
200
+ 25
3.465
+ 85
+ 125
55
10
Unit
MHz
ppm
V
°C
°C
%
mS
Tristate internal pull up,
output active when high
LVDS Levels Test Circuit
OUT
50
?
Vo
50
?
___
OUT
Dimensions are in mm
PIN
1
2
3
4
5
6
Function
OE (CMOS)
Do Not Connect
Ground
LVDS +
LVDS -
Vdd
Solder Pad Layout
Cardinal Components, Inc.
155 Route 46 West
Wayne, NJ 07470
Rev: C-090414-11
O-25
TEL:
(973)785-1333
E-MAIL: sales@cardinalxtal.com
WEB: http://www.cardinalxtal.com
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