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TPS2320
TPS2321
www.ti.com
SLVS276F – MARCH 2000 – REVISED JULY 2013
DUAL HOT SWAP POWER CONTROLLERS
WITH INDEPENDENT CIRCUIT BREAKER
Check for Samples:
TPS2320, TPS2321
1
FEATURES
Dual-Channel High-Side MOSFET Drivers
IN1: 3 V to 13 V; IN2: 3 V to 5.5 V
Output dV/dt Control Limits Inrush Current
Independent Circuit-Breaker With
Programmable Overcurrent Threshold and
Transient Timer
CMOS- and TTL-Compatible Enable Input
Low, 5-μA Standby Supply Current (Max)
Available in 16-Pin SOIC and TSSOP Package
–40°C to 85°C Ambient Temperature Range
Electrostatic Discharge Protection
GATE1
GATE2
DGND
TIMER
VREG
AGND
ISENSE2
ISENSE1
•
•
•
•
D OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
•
•
•
•
•
DISCH1
DISCH2
ENABLE
FAULT
ISET1
ISET2
IN2
IN1
NOTE: Terminal 14 is active-high on TPS2321.
typical application
V
O1
+
V1
3 V–13 V
IN1
VREG
ISET1
ISENSE1 GATE1
DISCH1
APPLICATIONS
•
•
•
Hot-Swap/Plug/Dock Power Management
Hot-Plug PCI, Device Bay
Electronic Circuit Breaker
AGND
DESCRIPTION
DGND
TPS2320
FAULT
TIMER
The TPS2320 and TPS2321 are dual-channel hot-
ENABLE
swap controllers that use external N-channel
GATE2
ISENSE2
DISCH2
IN2
ISET2
MOSFETs as high-side switches in power
applications. Features of these devices, such as
V
overcurrent protection (OCP), inrush-current control,
+
V2
3 V–5.5 V
and the ability to discriminate between load transients
and faults, are critical requirements for hot-swap
applications.
A
The TPS2320/21 devices incorporate undervoltage lockout (UVLO) to ensure the device is off at startup. Each
internal charge pump, capable of driving multiple MOSFETs, provides enough gate-drive voltage to fully enhance
the N-channel MOSFETs. The charge pumps control both the rise times and fall times (dv/dt) of the MOSFETs,
reducing power transients during power up/down. The circuit-breaker functionality combines the ability to sense
overcurrent conditions with a timer function; this allows designs such as DSPs, that may have high peak currents
during power-state transitions, to disregard transients for a programmable period.
O2
Table 1. AVAILABLE OPTIONS
T
A
HOT-SWAP CONTROLLER DESCRIPTION
Dual-channel with independent OCP and adjustable PG
Dual-channel with interdependent OCP and adjustable PG
–40°C to 85°C Dual-channel with independent OCP
Single-channel with OCP and adjustable PG
1
PIN
COUNT
20
20
16
14
PACKAGES
ENABLE
TPS2300IPW
TPS2310IPW
TPS2320ID
TPS2320IPW
TPS2330ID
TPS2330IPW
ENABLE
TPS2301IPW
TPS2311IPW
TPS2321ID
TPS2321IPW
TPS2331ID
TPS2331IPW
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2000–2013, Texas Instruments Incorporated
TPS2320
TPS2321
SLVS276F – MARCH 2000 – REVISED JULY 2013
www.ti.com
FUNCTIONAL BLOCK DIAGRAM
IN1
VREG
PREREG
ISET1
ISENSE1
GATE1
Clamp
dv/dt Rate
Protection
50
µA
UVLO and
Power Up
Circuit
Breaker
Charge
Pump
Pulldown FET
Circuit Breaker
75
µA
DISCH1
AGND
DGND
ENABLE
Deglitcher
Logic
FAULT
TIMER
Second Channel
IN2
ISET2
ISENSE2
GATE2
DISCH2
Table 2. Terminal Functions
TERMINAL
NAME
AGND
DGND
DISCH1
DISCH2
ENABLE/ENABLE
FAULT
GATE1
GATE2
IN1
IN2
ISENSE1
ISENSE2
ISET1
ISET2
TIMER
VREG
NO.
6
3
16
15
14
13
1
2
9
10
8
7
12
11
4
5
I/O
I
I
O
O
I
O
O
O
I
I
I
I
I
I
O
O
DESCRIPTION
Analog ground, connects to DGND as close as possible
Digital ground
Discharge transistor 1
Discharge transistor 2
Active low (TPS2320) or active high enable (TPS2321)
Overcurrent fault, open-drain output
Connects to gate of channel 1 high-side MOSFET
Connects to gate of channel 2 high-side MOSFET
Input voltage for channel 1
Input voltage for channel 2
Current-sense input channel 1
Current-sense input channel 2
Adjusts circuit-breaker threshold with resistor connected to IN1
Adjusts circuit-breaker threshold with resistor connected to IN2
Adjusts circuit-breaker deglitch time
Connects to bypass capacitor, for stable operation
2
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TPS2320 TPS2321
Copyright © 2000–2013, Texas Instruments Incorporated
TPS2320
TPS2321
www.ti.com
SLVS276F – MARCH 2000 – REVISED JULY 2013
DETAILED DESCRIPTION
DISCH1, DISCH2 –
DISCH1 and DISCH2 should be connected to the sources of the external N-channel
MOSFET transistors connected to GATE1 and GATE2, respectively. These pins discharge the loads when the
MOSFET transistors are disabled. They also serve as reference-voltage connections for internal gate voltage-
clamp circuitry.
ENABLE or ENABLE –
ENABLE for TPS2320 is active low. ENABLE for TPS2321 is active high. When the
controller is enabled, both GATE1 and GATE2 voltages will power up to turn on the external MOSFETs. When
the ENABLE pin is pulled high for TPS2320 or the ENABLE pin is pulled low for TPS2321 for more than 50 µs,
the gate of the MOSFET is discharged at a controlled rate by a current source, and a transistor is enabled to
discharge the output bulk capacitance. In addition, the device turns on the internal regulator PREREG (see
VREG) when enabled and shuts down PREREG when disabled so that total supply current is much less than
5μA.
FAULT –
FAULT is an open-drain overcurrent flag output. When an overcurrent condition in either channel is
sustained long enough to charge TIMER to 0.5 V, the overcurrent channel latches off and pulls FAULT low. The
other channel will run normally if not in overcurrent. In order to turn the channel back on, either the enable pin
has to be toggled or the input power has to be cycled.
GATE1, GATE2 –
GATE1 and GATE2 connect to the gates of external N-channel MOSFET transistors. When
the device is enabled, internal charge-pump circuitry pulls these pins up by sourcing approximately 15μA to each.
The turnon slew rates depend upon the capacitance present at the GATE1 and GATE2 terminals. If desired, the
turnon slew rates can be further reduced by connecting capacitors between these pins and ground. These
capacitors also reduce inrush current and protect the device from false overcurrent triggering during power up.
The charge-pump circuitry will generate gate-to-source voltages of 9 V-12 V across the external MOSFET
transistors.
IN1, IN2 –
IN1 and IN2 should be connected to the power sources driving the external N-channel MOSFET
transistors connected to GATE1 and GATE2, respectively. The TPS2320/TPS2321 draws its operating current
from IN1, and both channels will remain disabled until the IN1 power supply has been established. The IN1
channel has been constructed to support 3-V, 5-V, or 12-V operation, while the IN2 channel has been
constructed to support 3-V or 5-V operation
ISENSE1, ISENSE2, ISET1, ISET2 –
ISENSE1 and ISENSE2, in combination with ISET1 and ISET2, implement
overcurrent sensing for GATE1 and GATE2. ISET1 and ISET2 set the magnitude of the current that generates
an overcurrent fault, through external resistors connected to ISET1 and ISET2. An internal current source draws
50 µA from ISET1 and ISET2. With a sense resistor from IN1 to ISENSE1 or from IN2 to ISENSE2, which is also
connected to the drains of external MOSFETs, the voltage on the sense resistor reflects the load current. An
overcurrent condition is assumed to exist if ISENSE1 is pulled below ISET1 or if ISENSE2 is pulled below ISET2.
To ensure proper circuit breaker operation, V
I(ISENSE1)
and V
I(ISET1)
should never exceed V
I(IN1)
. Similarly,
V
I(ISENSE2)
and V
I(ISET2)
should never exceed V
I(IN2)
.
TIMER –
A capacitor on TIMER sets the time during which the power switch can be in overcurrent before turning
off. When the overcurrent protection circuits sense an excessive current, a current source is enabled which
charges the capacitor on TIMER. Once the voltage on TIMER reaches approximately 0.5 V, the circuit-breaker
latch is set and the power switch is latched off. Power must be recycled or the ENABLE pin must be toggled to
restart the controller. In high-power or high-temperature applications, a minimum 50-pF capacitor is strongly
recommended from TIMER to ground, to prevent any false triggering.
VREG –
VREG is the output of an internal low-dropout voltage regulator, where IN1 is the input. The regulator is
used to generate a regulated voltage source, less than 5.5 V, for the device. A 0.1-μF ceramic capacitor should
be connected between VREG and ground to aid in noise rejection. In this configuration, upon disabling the
device, the internal low-dropout regulator will also be disabled, which removes power from the internal circuitry
and allows the device to be placed in low-quiescent-current mode. In applications where IN1 is less than5.5 V,
VREG and IN1 may be connected together. However, under these conditions, disabling the device will not place
the device in low-quiescent-current mode, because the internal low-dropout voltage regulator is being bypassed,
thereby keeping internal circuitry operational. If VREG and IN1 are connected together, a 0.1-μF ceramic
capacitor between VREG and ground is not needed if IN1 already has a bypass capacitor of 1μF to 10μF.
Copyright © 2000–2013, Texas Instruments Incorporated
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TPS2320 TPS2321
3
TPS2320
TPS2321
SLVS276F – MARCH 2000 – REVISED JULY 2013
www.ti.com
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
V
I(IN1)
, V
I(ISENSE1)
, V
I(ISET1)
, V
I(ENABLE)
V
I(IN2)
, V
I(ISENSE2)
, V
I(ISET2)
, V
I(VREG)
V
O(GATE1)
Output voltage range
V
O(GATE2)
V
O(DISCH1)
, V
O(FAULT)
, V
O(DISCH2)
, V
O(TIMER)
Sink current range
I
(GATE1)
, I
(GATE2)
, I
(DISCH1)
, I
(DISCH2)
I
(TIMER)
, I
(FAULT)
(1) (2)
VALUE
Input voltage range
–0.3 to 15
–0.3 to 7
–0.3 to 30
–0.3 to 22
–0.3 to 15
0 to 100
0 to 10
–40 to 100
–55 to 150
260
UNIT
V
V
V
V
V
mA
mA
°C
°C
°C
Operating virtual junction temperature range, T
J
Storage temperature range, T
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
(2)
Stresses beyond those listed under
absolute maximum ratings
may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under
recommended operating
conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are respect to DGND.
DISSIPATION RATING TABLE
PACKAGE
PW-16
D-16
T
A
≤
25°C
POWER RATING
823 mW
674 mW
DERATING FACTOR
ABOVE T
A
= 25°C
10.98 mW/°C
8.98 mW/°C
T
A
= 70°C
POWER RATING
329 mW
270 mW
T
A
= 85°C
POWER RATING
165 mW
135 mW
RECOMMENDED OPERATING CONDITIONS
MIN
V
I(IN1)
, V
I(ISENSE1)
, V
I(ISET1)
V
I
Input voltage
V
I(IN2)
, V
I(ISENSE2)
, V
I(ISET2)
, V
I(VREG)
V
I(ISENSE1)
, V
I(ISET1)
V
I(ISENSE2)
, V
I(ISET2)
T
J
Operating virtual junction temperature
–40
3
3
NOM
MAX
13
5.5
V
I(IN1)
V
I(IN2)
100
°C
V
UNIT
4
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TPS2320 TPS2321
Copyright © 2000–2013, Texas Instruments Incorporated
Analog electronics
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