TPS2320IDR datasheet, PDF - EEWORLD Datasheet

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TPS2320IDR: Description2-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO16, GREEN, PLASTIC, MS-012AC, SOIC-16; CategoryPower/power management The power supply circuit; File Size1MB，27 Pages; ManufacturerRochester Electronics; Websitehttps://www.rocelec.com/; Environmental Compliance

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TPS2320IDR Overview

2-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO16, GREEN, PLASTIC, MS-012AC, SOIC-16

TPS2320IDR Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Parts packaging code	SOIC
package instruction	GREEN, PLASTIC, MS-012AC, SOIC-16
Contacts	16
Reach Compliance Code	unknown
Other features	REQUIRES 3V TO 5.5V SUPPLY FOR CHANNEL 2
Adjustable threshold	YES
Analog Integrated Circuits - Other Types	POWER SUPPLY SUPPORT CIRCUIT
JESD-30 code	R-PDSO-G16
JESD-609 code	e4
length	9.9 mm
Humidity sensitivity level	1
Number of channels	2
Number of functions	1
Number of terminals	16
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	260
Maximum seat height	1.75 mm
Maximum supply voltage (Vsup)	13 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	4.5 V
surface mount	YES
Temperature level	INDUSTRIAL
Terminal surface	NICKEL PALLADIUM GOLD
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	3.9 mm
Base Number Matches	1

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TPS2320

TPS2321

www.ti.com

SLVS276F – MARCH 2000 – REVISED JULY 2013

DETAILED DESCRIPTION

DISCH1, DISCH2 –

DISCH1 and DISCH2 should be connected to the sources of the external N-channel

MOSFET transistors connected to GATE1 and GATE2, respectively. These pins discharge the loads when the

MOSFET transistors are disabled. They also serve as reference-voltage connections for internal gate voltage-

clamp circuitry.

ENABLE or ENABLE –

ENABLE for TPS2320 is active low. ENABLE for TPS2321 is active high. When the

controller is enabled, both GATE1 and GATE2 voltages will power up to turn on the external MOSFETs. When

the ENABLE pin is pulled high for TPS2320 or the ENABLE pin is pulled low for TPS2321 for more than 50 µs,

the gate of the MOSFET is discharged at a controlled rate by a current source, and a transistor is enabled to

discharge the output bulk capacitance. In addition, the device turns on the internal regulator PREREG (see

VREG) when enabled and shuts down PREREG when disabled so that total supply current is much less than

5μA.

FAULT –

FAULT is an open-drain overcurrent flag output. When an overcurrent condition in either channel is

sustained long enough to charge TIMER to 0.5 V, the overcurrent channel latches off and pulls FAULT low. The

other channel will run normally if not in overcurrent. In order to turn the channel back on, either the enable pin

has to be toggled or the input power has to be cycled.

GATE1, GATE2 –

GATE1 and GATE2 connect to the gates of external N-channel MOSFET transistors. When

the device is enabled, internal charge-pump circuitry pulls these pins up by sourcing approximately 15μA to each.

The turnon slew rates depend upon the capacitance present at the GATE1 and GATE2 terminals. If desired, the

turnon slew rates can be further reduced by connecting capacitors between these pins and ground. These

capacitors also reduce inrush current and protect the device from false overcurrent triggering during power up.

The charge-pump circuitry will generate gate-to-source voltages of 9 V-12 V across the external MOSFET

transistors.

IN1, IN2 –

IN1 and IN2 should be connected to the power sources driving the external N-channel MOSFET

transistors connected to GATE1 and GATE2, respectively. The TPS2320/TPS2321 draws its operating current

from IN1, and both channels will remain disabled until the IN1 power supply has been established. The IN1

channel has been constructed to support 3-V, 5-V, or 12-V operation, while the IN2 channel has been

constructed to support 3-V or 5-V operation

ISENSE1, ISENSE2, ISET1, ISET2 –

ISENSE1 and ISENSE2, in combination with ISET1 and ISET2, implement

overcurrent sensing for GATE1 and GATE2. ISET1 and ISET2 set the magnitude of the current that generates

an overcurrent fault, through external resistors connected to ISET1 and ISET2. An internal current source draws

50 µA from ISET1 and ISET2. With a sense resistor from IN1 to ISENSE1 or from IN2 to ISENSE2, which is also

connected to the drains of external MOSFETs, the voltage on the sense resistor reflects the load current. An

overcurrent condition is assumed to exist if ISENSE1 is pulled below ISET1 or if ISENSE2 is pulled below ISET2.

To ensure proper circuit breaker operation, V

I(ISENSE1)

and V

I(ISET1)

should never exceed V

I(IN1)

. Similarly,

I(ISENSE2)

and V

I(ISET2)

should never exceed V

I(IN2)

TIMER –

A capacitor on TIMER sets the time during which the power switch can be in overcurrent before turning

off. When the overcurrent protection circuits sense an excessive current, a current source is enabled which

charges the capacitor on TIMER. Once the voltage on TIMER reaches approximately 0.5 V, the circuit-breaker

latch is set and the power switch is latched off. Power must be recycled or the ENABLE pin must be toggled to

restart the controller. In high-power or high-temperature applications, a minimum 50-pF capacitor is strongly

recommended from TIMER to ground, to prevent any false triggering.

VREG –

VREG is the output of an internal low-dropout voltage regulator, where IN1 is the input. The regulator is

used to generate a regulated voltage source, less than 5.5 V, for the device. A 0.1-μF ceramic capacitor should

be connected between VREG and ground to aid in noise rejection. In this configuration, upon disabling the

device, the internal low-dropout regulator will also be disabled, which removes power from the internal circuitry

and allows the device to be placed in low-quiescent-current mode. In applications where IN1 is less than5.5 V,

VREG and IN1 may be connected together. However, under these conditions, disabling the device will not place

the device in low-quiescent-current mode, because the internal low-dropout voltage regulator is being bypassed,

thereby keeping internal circuitry operational. If VREG and IN1 are connected together, a 0.1-μF ceramic

capacitor between VREG and ground is not needed if IN1 already has a bypass capacitor of 1μF to 10μF.

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TPS2320 TPS2321

TPS2320IDR Related Products

	TPS2320IDR	TPS2320ID	TPS2321ID	TPS2321IPW
Description	2-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO16, GREEN, PLASTIC, MS-012AC, SOIC-16	2-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO16, GREEN, PLASTIC, MS-012AC, SOIC-16	2-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO16, GREEN, PLASTIC, MS-012AC, SOIC-16	2-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO16, GREEN, PLASTIC, TSSOP-16
Is it lead-free?	Lead free	Lead free	Lead free	Lead free
Is it Rohs certified?	conform to	conform to	conform to	conform to
Parts packaging code	SOIC	SOIC	SOIC	TSSOP
package instruction	GREEN, PLASTIC, MS-012AC, SOIC-16	GREEN, PLASTIC, MS-012AC, SOIC-16	GREEN, PLASTIC, MS-012AC, SOIC-16	GREEN, PLASTIC, TSSOP-16
Contacts	16	16	16	16
Reach Compliance Code	unknown	unknown	unknown	unknown
Other features	REQUIRES 3V TO 5.5V SUPPLY FOR CHANNEL 2	REQUIRES 3V TO 5.5V SUPPLY FOR CHANNEL 2	REQUIRES 3V TO 5.5V SUPPLY FOR CHANNEL 2	REQUIRES 3V TO 5.5V SUPPLY FOR CHANNEL 2
Adjustable threshold	YES	YES	YES	YES
Analog Integrated Circuits - Other Types	POWER SUPPLY SUPPORT CIRCUIT	POWER SUPPLY SUPPORT CIRCUIT	POWER SUPPLY SUPPORT CIRCUIT	POWER SUPPLY SUPPORT CIRCUIT
JESD-30 code	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16
JESD-609 code	e4	e4	e4	e4
length	9.9 mm	9.9 mm	9.9 mm	5 mm
Humidity sensitivity level	1	1	1	1
Number of channels	2	2	2	2
Number of functions	1	1	1	1
Number of terminals	16	16	16	16
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SOP	SOP	SOP	TSSOP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	260	260	260	260
Maximum seat height	1.75 mm	1.75 mm	1.75 mm	1.2 mm
Maximum supply voltage (Vsup)	13 V	13 V	13 V	13 V
Minimum supply voltage (Vsup)	3 V	3 V	3 V	3 V
Nominal supply voltage (Vsup)	4.5 V	4.5 V	4.5 V	4.5 V
surface mount	YES	YES	YES	YES
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal surface	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	1.27 mm	1.27 mm	1.27 mm	0.65 mm
Terminal location	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	3.9 mm	3.9 mm	3.9 mm	4.4 mm

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