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EPM5130JM

Description
UV PLD, 55ns, 128-Cell, CMOS, CQCC84, WINDOWED, CERAMIC, LCC-84
CategoryProgrammable logic devices    Programmable logic   
File Size261KB,10 Pages
ManufacturerAltera (Intel)
Download Datasheet Parametric View All

EPM5130JM Overview

UV PLD, 55ns, 128-Cell, CMOS, CQCC84, WINDOWED, CERAMIC, LCC-84

EPM5130JM Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
Parts packaging codeLCC
package instructionWQCCJ, LDCC84,1.2SQ
Contacts84
Reach Compliance Codeunknown
Other featuresLABS INTERCONNECTED BY PIA; 8 LABS; 128 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK
maximum clock frequency33.3 MHz
In-system programmableNO
JESD-30 codeS-CQCC-J84
JESD-609 codee0
JTAG BSTNO
length29.21 mm
Dedicated input times19
Number of I/O lines48
Number of macro cells128
Number of terminals84
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize19 DEDICATED INPUTS, 48 I/O
Output functionMACROCELL
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeWQCCJ
Encapsulate equivalent codeLDCC84,1.2SQ
Package shapeSQUARE
Package formCHIP CARRIER, WINDOW
Peak Reflow Temperature (Celsius)220
power supply5 V
Programmable logic typeUV PLD
propagation delay55 ns
Certification statusNot Qualified
Maximum seat height5.08 mm
Maximum supply voltage5.5 V
Minimum supply voltage4.5 V
Nominal supply voltage5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width29.21 mm
Base Number Matches1

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