TC74VHC175F/FT/FK
TOSHIBA CMOS Digital Integrated Circuit
Silicon Monolithic
TC74VHC175F, TC74VHC175FT, TC74VHC175FK
Quad D-Type Flip Flop with Clear
TC74VHC175F
The TC74VHC175 is an advanced high speed CMOS QUAD
D-TYPE FLIP FLOP fabricated with silicon gate C
2
MOS
technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low power
dissipation.
These four flip-flops are controlled by a clock input (CK) and a
clear input (
CLR
).
The information data applied to the D inputs (D1 thru D4) are
transferred to the outputs (Q1 thru Q4 and Q1 thru Q4 ) on the
positive-going edge of the clock pulse.
When the
CLR
input is held low, the Q outputs are at the low
logic level and the Q outputs are at the high logic level,
regardless of other input conditions.
An input protection circuit ensures that 0 to 5.5 V can be
applied to the input pins without regard to the supply voltage.
This device can be used to interface 5 V to 3 V systems and two
supply systems such as battery back up. This circuit prevents
device destruction due to mismatched supply and input voltages.
TC74VHC175FT
TC74VHC175FK
Features
•
•
•
•
•
•
•
•
High speed: f
max
=
210 MHz (typ.) at V
CC
=
5 V
Low power dissipation: I
CC
=
4
μA
(max) at Ta
=
25°C
High noise immunity: V
NIH
=
V
NIL
=
28% V
CC
(min)
Power down protection is provided on all inputs.
Balanced propagation delays: t
pLH
∼
t
pHL
−
Wide operating voltage range: V
CC (opr)
=
2 to 5.5 V
Low noise: V
OLP
=
0.8 V (max)
Pin and function compatible with 74ALS175
Weight
SOP16-P-300-1.27A
TSSOP16-P-0044-0.65A
VSSOP16-P-0030-0.50
: 0.18 g (typ.)
: 0.06 g (typ.)
: 0.02 g (typ.)
Start of commercial production
1991-11
1
2014-03-01
TC74VHC175F/FT/FK
Absolute Maximum Ratings (Note)
Characteristics
Supply voltage range
DC input voltage
DC output voltage
Input diode current
Output diode current
DC output current
DC V
CC
/ground current
Power dissipation
Storage temperature
Symbol
V
CC
V
IN
V
OUT
I
IK
I
OK
I
OUT
I
CC
P
D
T
stg
Rating
−0.5
to 7.0
−0.5
to 7.0
−0.5
to V
CC
+ 0.5
−20
±20
±25
±50
180
−65
to 150
Unit
V
V
V
mA
mA
mA
mA
mW
°C
Note:
Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or
even destruction.
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly
even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute
maximum ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
Operating Range (Note)
Characteristics
Supply voltage
Input voltage
Output voltage
Operating temperature
Input rise and fall time
Symbol
V
CC
V
IN
V
OUT
T
opr
dt/dv
Rating
2.0 to 5.5
0 to 5.5
0 to V
CC
−40
to 85
0 to 100 (V
CC
= 3.3 ± 0.3 V)
0 to 20 (V
CC
= 5 ± 0.5 V)
Unit
V
V
V
°C
ns/V
Note:
The operating range must be maintained to ensure the normal operation of the device.
Unused inputs must be tied to either V
CC
or GND.
3
2014-03-01
TC74VHC175F/FT/FK
AC Characteristics
(input: t
r
= t
f
= 3 ns)
Characteristics
Symbol
Test Condition
V
CC
(V)
Propagation delay
time
(CK-Q,
Q
)
3.3 ± 0.3
―
5.0 ± 0.5
C
L
(pF)
15
50
15
50
15
50
15
50
15
50
15
50
50
50
Min
―
―
―
―
―
―
―
―
90
50
150
85
―
―
―
(Note 2)
―
Ta = 25°C
Typ.
7.5
10.0
4.8
6.3
6.3
8.8
4.3
5.8
140
75
210
115
―
―
4
44
Max
11.5
15.0
7.3
9.3
10.1
13.6
6.4
8.4
―
―
―
―
1.5
1.0
10
―
Ta =
−40
to
85°C
Min
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
75
45
125
75
―
―
―
―
Max
13.5
17.0
8.5
10.5
12.0
15.5
7.5
9.5
―
―
―
―
1.5
1.0
10
―
ns
pF
pF
MHz
ns
ns
Unit
t
pLH
t
pHL
Propagation delay
time
(
CLR
-Q,
Q
)
t
pLH
t
pHL
3.3 ± 0.3
―
5.0 ± 0.5
3.3 ± 0.3
Maximum clock
frequency
f
max
―
5.0 ± 0.5
t
osLH
t
osHL
C
IN
C
PD
3.3 ± 0.3
5.0 ± 0.5
―
Output to output skew
Input capacitance
Power dissipation
capacitance
(Note 1)
Note 1: Parameter guaranteed by design.
t
osLH
= |t
pLHm
−
t
pLHn
|, t
osHL
= |t
pHLm
−
t
pHLn
|
Note 2: C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load.
Average operating current can be obtained by the equation:
I
CC (opr)
= C
PD
·V
CC
·f
IN
+ I
CC
/4 (per bit)
And the total C
PD
when n pcs.of flip flop operate can be gained by the following equation:
C
PD
(total) = 30 + 14·n
Noise Characteristics
(input: t
r
= t
f
= 3 ns)
Characteristics
Quiet output maximum dynamic V
OL
Quiet output minimum dynamic V
OL
Minimum high level dynamic input voltage
Maximum low level dynamic input voltage
Symbol
V
OLP
V
OLV
V
IHD
V
ILD
C
L
= 50 pF
C
L
= 50 pF
C
L
= 50 pF
C
L
= 50 pF
Test Condition
V
CC
(V)
5.0
5.0
5.0
5.0
Ta = 25°C
Typ.
0.4
−0.4
―
―
Max
0.8
−0.8
3.5
1.5
Unit
V
V
V
V
5
2014-03-01
京公网安备 11010802033920号
EEWORLD
