MT46H64M32L2CG-54:A datasheet, PDF

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MT46H64M32L2CG-54:A: DescriptionDDR DRAM, 64MX32, 5ns, CMOS, PBGA152, 14 X 14 MM, 1 MM HEIGHT, GREEN, PLASTIC, VFBGA-152; Categorystorage storage; File Size274KB，12 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/; Environmental Compliance

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MT46H64M32L2CG-54:A Overview

DDR DRAM, 64MX32, 5ns, CMOS, PBGA152, 14 X 14 MM, 1 MM HEIGHT, GREEN, PLASTIC, VFBGA-152

MT46H64M32L2CG-54:A Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Parts packaging code	BGA
package instruction	VFBGA, BGA152,21X21,25
Contacts	152
Reach Compliance Code	compliant
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	5 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	185 MHz
I/O type	COMMON
interleaved burst length	2,4,8
JESD-30 code	S-PBGA-B152
length	14 mm
memory density	2147483648 bit
Memory IC Type	DDR DRAM
memory width	32
Number of functions	1
Number of ports	1
Number of terminals	152
word count	67108864 words
character code	64000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	64MX32
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	VFBGA
Encapsulate equivalent code	BGA152,21X21,25
Package shape	SQUARE
Package form	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
power supply	1.8 V
Certification status	Not Qualified
refresh cycle	8192
Maximum seat height	1 mm
self refresh	YES
Continuous burst length	2,4,8
Maximum supply voltage (Vsup)	1.95 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	BALL
Terminal pitch	0.65 mm
Terminal location	BOTTOM
width	14 mm
Base Number Matches	1

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152-Ball x32 Mobile LPDDR (only) PoP (TI-OMAP)

Features

Mobile LPDDR (only)

152-Ball Package-on-Package (PoP) TI-OMAP™

MT46HxxxMxxLxCG

MT46HxxxMxxLxKZ

Features

• V

DD/

DDQ

= 1.70–1.95V

• Bidirectional data strobe per byte of data (DQS)

• Internal, pipelined double data rate (DDR)

architecture; 2 data accesses per clock cycle

• Differential clock inputs (CK and CK#)

• Commands entered on each positive CK edge

• DQS edge-aligned with data for READs; center-

aligned with data for WRITEs

• 4 internal banks for concurrent operation

• Data masks (DM) for masking write data—one mask

per byte

• Programmable burst lengths (BLs): 2, 4, 8, or 16

• Concurrent auto precharge option is supported

• Auto refresh and self refresh modes

• 1.8V LVCMOS-compatible inputs

• On-chip temperature sensor to control self refresh

rate

• Partial-array self refresh (PASR)

• Deep power-down (DPD)

• STATUS REGISTER READ (SRR) supported

• Selectable output drive strength (DS)

• Clock stop capability

• 64ms refresh

Options

Marking

• V

DD/

DDQ

–

1.8V/1.8V

• Configuration

–

128 Meg x 32 (16 Meg x 16 x 4 banks x 4) 128M32

64M32

–

64 Meg x 32 (8 Meg x 32 x 4 banks x 2)

32M32

–

32 Meg x 32 (8 Meg x 32 x 4 banks)

16M32

–

16 Meg x 32 (4 Meg x 32 x 4 banks)

• Device version

–

Single die, standard addressing

–

2-die stack, standard addressing

–

4-die stack, standard addressing

• Plastic “green” package

–

152-ball VFBGA (14 x 14 x 1.0mm)

–

152-ball VFBGA (14 x 14 x 1.2mm)

• Timing – cycle time

–

5ns @ CL = 3

-5

–

5.4ns @ CL = 3

-54

-6

–

6ns @ CL = 3

• Operating temperature range

–

Commercial (0°C to +70°C)

None

–

Industrial (–40°C to +85°C)

Notes: 1. BL 16: contact factory for availability.

2. Contact factory for remapped SRR output.

Table 1:

Architecture

Configuration

Configuration Addressing

128 Meg x 32

16 Meg x 16

x 4 banks x 4 die

16K (A[13:0])

1K (A[9:0])

Notes:

64 Meg x 32

8 Meg x 32

x 4 banks x 2 die

8K (A[12:0])

1K (A[9:0])

32 Meg x 32

8 Meg x 32

x 4 banks

8K (A[12:0])

1K (A[9:0])

16 Meg x 32

4 Meg x 32

x 4 banks

8K (A[12:0])

512 (A[8:0])

Refresh count

Row addressing

Column addressing

1. Quad die stack. Each CS configured with two x16 die connected in parallel to make up a 32-bit-

wide bus.

PDF: 09005aef833913f1/Source: 09005aef833913d6

ddr_mobile_sdram_only_152b_omap_pop.fm - Rev. E 06/09 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

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