RTAX4000S-1LG1272EV datasheet, PDF

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RTAX4000S-1LG1272EV: DescriptionField Programmable Gate Array, 40320 CLBs, 4000000 Gates, CMOS, CBGA1272, LGA-1272; CategoryProgrammable logic devices Programmable logic; File Size14MB，278 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com

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RTAX4000S-1LG1272EV Overview

Field Programmable Gate Array, 40320 CLBs, 4000000 Gates, CMOS, CBGA1272, LGA-1272

RTAX4000S-1LG1272EV Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
package instruction	LGA-1272
Reach Compliance Code	compliant
Other features	500000 ASIC GATES ALSO AVAILABLE
Combined latency of CLB-Max	0.95 ns
JESD-30 code	S-CBGA-B1272
length	37.5 mm
Configurable number of logic blocks	40320
Equivalent number of gates	4000000
Number of entries	840
Output times	840
Number of terminals	1272
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	40320 CLBS, 4000000 GATES
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	LGA
Encapsulate equivalent code	LGA(UNSPEC)
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	1.5/3.3 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Filter level	MIL-PRF-38535
Maximum supply voltage	1.575 V
Minimum supply voltage	1.425 V
Nominal supply voltage	1.5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal form	BUTT
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	37.5 mm
Base Number Matches	1

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Revision 15

RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs

Radiation Performance

• SEU-Hardened Registers Eliminate the Need for Triple-Module

Redundancy (TMR)

– Immune to Single-Event Upsets (SEU) to LET

> 37 MeV-

/mg

– SEU Rate < 10

-10

Errors/Bit-Day (worst case GEO)

• SRAM Upset Rate of <10

-10

Errors/Bit-Day with Use of Error

Detection and Correction (EDAC) IP (included) with Integrated

SRAM Scrubber

– Single-Bit Correction, Double-Bit Detection

– Variable-Rate Background Refreshing

• Total Ionizing Dose Up to 300 krad (Si, Functional)

• Single-Event Latch-Up Immunity (SEL) to LET

> 117 MeV-

/mg

• TM1019 Test Data Available

Specifications

• Up to 4 Million Equivalent System Gates or 500 k Equivalent

ASIC Gates

• Up to 20,160 SEU-Hardened Flip-Flops

• Up to 840 I/Os

with

SEU-Protected Input, Output, and Enable

Registers

• Up to 540 kbits Embedded SRAM

• Manufactured on 0.15 µm CMOS Antifuse Process Technology,

7 Layers of Metal

• Electrostatic Discharge (ESD) is 2,000 V (HBM MIL-STD-883,

TM3015)

Embedded Multiply/Accumulate Blocks

(RTAX-DSP Only)

•

Up to 120 Multiply/Accumulate Blocks

Fully SEU- and SET-Hardened

125 MHz Performance throughout Military Temperature Range

Flexible, Cascadable Accumulate Function

Processing Flows

• B-Flow – MIL-STD-883B

• E-Flow – Extended Flow

• EV-Flow – Class V Equivalent Flow Processing Consistent with

MIL-PRF 38535 (RTAX-DSP only)

• V-Flow – QML Class V per MIL-PRF-38535 (RTAX-S/SL only)

Features

• Single-Chip, Nonvolatile Solution

• 1.5 V Core Voltage for Low Power

• Flexible, Multi-Standard I/Os:

– 1.5 V, 1.8 V, 2.5 V, 3.3 V Mixed Voltage Operation

– Bank-Selectable I/Os – 8 Banks per Chip

– Single-Ended I/O Standards: LVTTL, LVCMOS, 3.3 V PCI

– JTAG Boundary Scan Testing (as per IEEE 1149.1)

– Differential I/O Standards: LVPECL and LVDS

– Voltage-Referenced I/O Standards: GTL+, HSTL Class 1,

SSTL2 Class 1 and 2, SSTL3 Class 1 and 2

– Hot-Swap with Cold-Sparing Support (Except PCI)

• Embedded Memory with Variable Aspect Ratio:

– Independent, Width-Configurable Read and Write Ports

– Programmable Embedded FIFO Control Logic

– ROM Emulation Capability

• Deterministic, User-Controllable Timing

• Unique In-System Diagnostic and Debug Capability

Prototyping Options

• Commercial Axcelerator

Devices for Functional Verification

(RTAX™-S/SL only)

• RTAX-S/SL PROTO and RTAX-DSP PROTO Devices with

Same Functional and Timing Characteristics as Flight Unit in a

Non-Hermetic Package

• Low-Priced Reprogrammable ProASIC

3 Option for Functional

Verification (RTAX-S/SL only)

• Offers Up To 80% Saving of Static Current Compared to

Standard RTAX-S Device at Worst-Case Conditions

RTAX-SL Low Power Option

Leading-Edge Performance

•

High-Performance Embedded FIFOs

350+ MHz System Performance

500+ MHz Internal Performance

700 Mb/s LVDS Capable I/Os

Table 1 • RTAX Family Product Profile

Device

Capacity

Equivalent System Gates

ASIC Gates

Modules

Combinatorial (C-cells)

Embedded RAM/FIFO (w/o EDAC)

Core RAM Blocks

Core RAM Bits (K = 1,024)

Embedded Multiply/Accumulate

Blocks

Clocks (segmentable)

Hardwired

Routed

I/Os

I/O Banks

User I/Os (maximum)

I/O Registers

Package

CG/LG*

Note:

RTAX250S/SL RTAX1000S/SL RTAX2000S/SL RTAX4000S/SL RTAX2000D/DL RTAX4000D/DL

250,000

30,000

1,408

2,816

54 k

–

1,000,000

125,000

6,048

12,096

162 k

–

2,000,000

250,000

10,752

21,504

288 k

–

4,000,000

500,000

20,160

40,320

120

540 k

–

2,000,000

250,000

9,856

19,712

288 k

4,000,000

500,000

18,480

36,960

120

540 k

120

198

744

624

208, 352

418

1,548

624

352

684

2,052

624, 1152

256, 352

840

2,520

1272

352

684

2,052

1272

352

840

2,520

1272

352

*The body size of the CG1272 and LG1272 packages used on the RTAX-DSP devices is slightly larger than the body size of the

CG/LG1272 used on RTAX4000S/SL devices.

May 2012

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