GS8170LW36/72C-333/300/250/200
209-Bump BGA
Commercial Temp
Industrial Temp
Features
• Late Write mode, Pipelined Read mode
• JEDEC-standard SigmaRAM
™
pinout and package
• 1.8 V +150/–100 mV core power supply
• 1.8 V CMOS Interface
• ZQ controlled user-selectable output drive strength
• Dual Cycle Deselect
• Burst Read and Write option
• Fully coherent read and write pipelines
• Echo Clock outputs track data output drivers
• Byte write operation (9-bit bytes)
• 2 user-programmable chip enable inputs
• IEEE 1149.1 JTAG-compliant Serial Boundary Scan
• 209-bump, 14 mm x 22 mm, 1 mm bump pitch BGA package
• Pin-compatible with future 36Mb, 72Mb, and 144Mb
devices
18Mb
Σ
1x1Lp CMOS I/O
Late Write SigmaRAM™
Functional Description
200 MHz–333 MHz
1.8 V V
DD
1.8 V I/O
SigmaRAM Family Overview
GS8170LW36/72 SigmaRAMs are built in compliance with
the SigmaRAM pinout standard for synchronous SRAMs.
They are 18,874,368-bit (18Mb) SRAMs. This family of wide,
very low voltage CMOS I/O SRAMs is designed to operate at
the speeds needed to implement economical high performance
networking systems.
Bottom View
209-Bump, 14 mm x 22 mm BGA
1 mm Bump Pitch, 11 x 19 Bump Array
Because SigmaRAMs are synchronous devices, address data
inputs and read/write control inputs are captured on the rising
edge of the input clock. Write cycles are internally self-timed
and initiated by the rising edge of the clock input. This feature
eliminates complex off-chip write pulse generation required by
asynchronous SRAMs and simplifies input signal timing.
Σ
RAMs support pipelined reads utilizing a rising-edge-
triggered output register. They also utilize a Dual Cycle
Deselect (DCD) output deselect protocol.
Σ
RAMs are offered in a number of configurations including
Late Write, Double Late Write, and Double Data Rate (DDR).
The logical differences between the protocols employed by
these RAMs mainly involve various approaches to write
cueing and data transfer rates. The
Σ
RAM
™
family standard
allows a user to implement the interface protocol best suited to
the task at hand.
Σ
RAMs are implemented with high performance CMOS
technology and are packaged in a 209-bump BGA.
Parameter Synopsis
Key Fast Bin Specs
Cycle Time
Access Time
Symbol
tKHKH
tKHQV
- 333
3.0 ns
1.6 ns
Rev: 2.03 1/2005
1/27
© 2002, GSI Technology, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8170LW36/72C-333/300/250/200
256K x 72 Common I/O—Top View (Package C)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
• 2002.06
•
2
DQg
DQg
DQg
DQg
DQc
DQc
DQc
DQc
DQc
CQ2
DQh
DQh
DQh
DQh
DQh
DQd
DQd
DQd
DQd
3
A
Bc
Bh
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
CK
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
NC
A
TMS
4
E2
Bg
Bd
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
A
A
TDI
5
A
NC
NC
(144M)
NC
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
NC
NC
(72M)
A
A
6
ADV
W
E1
MCL
V
DD
ZQ
EP2
EP3
MCL
MCL
MCH
7
A
A
NC
NC
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
8
E3
Bb
Be
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
A
A
TDO
9
A
Bf
Ba
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
NC
A
TCK
10
DQb
DQb
DQb
DQb
DQf
DQf
DQf
DQf
DQf
CQ1
DQa
DQa
DQa
DQa
DQa
DQe
DQe
DQe
DQe
11
DQb
DQb
DQb
DQb
DQb
DQf
DQf
DQf
DQf
CQ1
DQa
DQa
DQa
DQa
DQe
DQe
DQe
DQe
DQe
DQg
DQg
DQg
DQg
DQg
DQc
DQc
DQc
DQc
CQ2
DQh
DQh
DQh
DQh
DQd
DQd
DQd
DQd
DQd
MCH
MCL
V
DD
MCL
A
A1
A0
V
DD
V
SS
V
DD
NC
NC
(36M)
A
A
11 x 19 Bump BGA—14 x 22 mm
2
Body—1 mm Bump Pitch
Note:
Users of CMOS I/O SigmaRAMs may wish to connect “NC, V
REF
” and the “NC, CK” pins to V
REF
(i.e., V
DDQ
/2) to allow alternate
use of future HSTL I/O SigmaRAMs.
Rev: 2.03 1/2005
2/27
© 2002, GSI Technology, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8170LW36/72C-333/300/250/200
512K x 36 Common I/O—Top View (Package C)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
• 2002.06
•
2
NC
NC
NC
NC
DQc
DQc
DQc
DQc
DQc
CQ2
NC
NC
NC
NC
NC
DQd
DQd
DQd
DQd
3
A
Bc
NC
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
CK
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
NC
A
TMS
4
E2
NC
Bd
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
A
A
TDI
5
A
A
NC
(144M)
NC
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
NC
NC
(72M)
A
A
6
ADV
W
E1
MCL
V
DD
ZQ
EP2
EP3
MCL
MCL
MCH
MCH
MCH
MCL
V
DD
MCL
A
A1
A0
7
A
A
NC
NC
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
NC
NC
(36M)
A
A
8
E3
Bb
NC
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
A
A
TDO
9
A
NC
Ba
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
NC
A
TCK
10
DQb
DQb
DQb
DQb
NC
NC
NC
NC
NC
CQ1
DQa
DQa
DQa
DQa
DQa
NC
NC
NC
NC
11
DQb
DQb
DQb
DQb
DQb
NC
NC
NC
NC
CQ1
DQa
DQa
DQa
DQa
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
DQc
DQc
DQc
DQc
CQ2
NC
NC
NC
NC
DQd
DQd
DQd
DQd
DQd
11 x 19 Bump BGA—14 x 22 mm
2
Body—1 mm Bump Pitch
Note:
Users of CMOS I/O SigmaRAMs may wish to connect “NC, V
REF
” and the “NC, CK” pins to V
REF
(i.e., V
DDQ
/2) to allow alternate
use of future HSTL I/O SigmaRAMs.
Rev: 2.03 1/2005
3/27
© 2002, GSI Technology, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8170LW36/72C-333/300/250/200
Pin Description Table
Symbol
A
ADV
Bx
W
E1
E2 & E3
EP2 & EP3
CK
CQ, CQ
DQ
MCH
MCL
Description
Address
Advance
Byte Write Enable
Write Enable
Chip Enable
Chip Enable
Chip Enable Program Pin
Clock
Echo Clock
Data I/O
Must Connect High
Must Connect Low
Type
Input
Input
Input
Input
Input
Input
Mode Input
Input
Output
Input/Output
Input
Input
Comments
—
Active High
Active Low
Active Low
Active Low
Programmable Active High or Low
To be tied directly to V
DD
, V
DDQ
or V
SS
Active High
Three State - Deselect via E2 or E3 False
Three State
Active High
To be tied directly to V
DD
or V
DDQ
Active Low
To be tied directly to V
SS
Low = Low Impedance [High Drive]
High = High Impedance [Low Drive]
To be tied directly to V
DDQ
or V
SS
Active High
—
—
—
Not connected to die or any other pin
1.8 V Nominal
1.8 V Nominal
—
ZQ
TCK
TDI
TDO
TMS
NC
V
DD
V
DDQ
V
SS
Output Impedance Control
Test Clock
Test Data In
Test Data Out
Test Mode Select
No Connect
Core Power Supply
Output Driver Power Supply
Ground
Mode Input
Input
Input
Output
Input
—
Input
Input
Input
Operation Control
All address, data and control inputs (with the exception of EP2, EP3, ZQ, and the mode pins, L6, M6, and J6) are synchronized to
rising clock edges. Data in is captured on both rising and falling edges of CK. Read and write operations must be initiated with the
Advance/Load pin (ADV) held low, in order to load the new address. Device activation is accomplished by asserting all three of
the Chip Enable inputs (E1, E2, and E3). Deassertion of any one of the Enable inputs will deactivate the device.
It should be noted
that ONLY deactivation of the RAM via E2 and/or E3 deactivates the Echo Clocks, CQ1–CQ2.
Rev: 2.03 1/2005
4/27
© 2002, GSI Technology, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8170LW36/72C-333/300/250/200
Read Operations
Pipelined Read
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1, E2,
and E3) are active, the write enable input signal (W) is deasserted high, and ADV is asserted low. The address presented to the
address inputs is latched into the address register and presented to the memory core and control logic. The control logic determines
that a read access is in progress and allows the requested data to propagate to the input of the output register. At the next rising edge
of clock the read data is allowed to propagate through the output register and onto the output pins
Single Data Rate (SDR) Pipelined Read.
Read A
CK
Address
ADV
E1
W
DQ
CQ
Q(A)
Q(B)
Q(C)
Q(D)
A
B
C
D
E
Deselect
Read B
Read C
Read D
Write Operations
Write operation occurs when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1, E2, and
E3) are active, the write enable input signal (W) is asserted low, and ADV is asserted low.
Late Write
In Late Write mode the RAM requires Data In one rising clock edge later than the edge used to load Address and Control. Late
Write protocol has been employed on SRAMs designed for RISC processor L2 cache applications and in Flow Through mode NBT
SRAMs
SigmaRAM Late Write with Pipelined Read
Read A
CK
Address
ADV
E1
Bx
W
DQ
CQ
Q(A)
D(B)
Q(C)
Q(D)
A
B
C
D
E
Deselect
Write B
Read C
Read D
Rev: 2.03 1/2005
5/27
© 2002, GSI Technology, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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