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Revision 2.0 (02-14-13)
DATASHEET
2
SMSC LAN9313/LAN9313i
Three Port 10/100 Managed Ethernet Switch with MII
Digital Reset (DIGITAL_RST) ......................................................................................................................................................................... 45
Port 2 PHY Reset............................................................................................................................................................................................ 46
Port 1 PHY Reset............................................................................................................................................................................................ 46
Spanning Tree Port State Override................................................................................................................................................................. 69
MAC Destination Address Lookup Priority...................................................................................................................................................... 69
Port Default Priority......................................................................................................................................................................................... 74
IP Precedence Based Priority ......................................................................................................................................................................... 74
DIFFSERV Based Priority............................................................................................................................................................................... 74
Packets from the Host CPU ............................................................................................................................................................................ 80
Packets to the Host CPU ................................................................................................................................................................................ 81
Buffer Limits and Flow Control Levels ............................................................................................................................................................ 81
MII MAC Interface ........................................................................................................................................................................................... 89
Scrambler and PISO ....................................................................................................................................................................................... 91
Revision 2.0 (02-14-13)
DATASHEET
4
SMSC LAN9313/LAN9313i
Three Port 10/100 Managed Ethernet Switch with MII
Datasheet
7.2.1.4
7.2.1.5
7.2.1.6
7.2.2.1
7.2.2.2
7.2.2.3
7.2.2.4
7.2.2.5
7.2.2.6
7.2.2.7
7.2.3.1
7.2.3.2
NRZI and MLT-3 Encoding ............................................................................................................................................................................. 91
100M Transmit Driver ..................................................................................................................................................................................... 91
100M Phase Lock Loop (PLL) ........................................................................................................................................................................ 91
DSP: Equalizer, BLW Correction and Clock/Data Recovery .......................................................................................................................... 92
NRZI and MLT-3 Decoding ............................................................................................................................................................................. 93
Descrambler and SIPO ................................................................................................................................................................................... 93
MII MAC Interface ........................................................................................................................................................................................... 93
MII MAC Interface ........................................................................................................................................................................................... 94
10M TX Driver and PLL .................................................................................................................................................................................. 94
Filter and Squelch ........................................................................................................................................................................................... 94
10M RX and PLL............................................................................................................................................................................................. 94
MII MAC Interface ........................................................................................................................................................................................... 95
Half Vs. Full-Duplex ........................................................................................................................................................................................ 98
PHY General Power-Down ........................................................................................................................................................................... 100
PHY Energy Detect Power-Down ................................................................................................................................................................. 100
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