SC652
Clock Generator for Pentium Based Designs W/2 DIMM Support
Approved Product
PRODUCT FEATURES
SEL1
FREQUENCY TABLE
SEL0
0
1
0
1
CPU
55.0
75.0
60.0
66.6
PCI
27.5
37.5
30.0
33.3
0
0
1
1
T
T
T
T
T
T
T
T
T
Supports Pentium® series, 6X86 and K6 CPUs.
Supports Intel VIA, SiS and Opti chipset
requirements.
Supports Sychronous DRAM designs
4 host (CPU/AGP) clocks & 8 SDRAM clocks.
Optional common or mixed supply mode :
(Vdd = Vddq3 = Vddq4 = Vddq2 = 3.3V)
(Vdd = Vddq3 = Vddq4 = 3.3V, Vddq2 = 2.5V)
< 250 pS skew on CPU buffers
< 250 pS skew on PCI buffers
Supports Single Pin Power Management.
48 Pin SSOP package for minimum board space
CONNECTION DIAGRAM
REF1
REF0
Vss
Xin
Xout
N/C
Vddq4
PCICLK_F
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Vdd
REF2
Vddq2
IOAPIC
PWR_DWN#
Vss
CPUCLK0
CPUCLK1
Vddq2
CPUCLK2
CPUCLK3
Vss
SDRAM0
SDRAM1
Vddq3
SDRAM2
SDRAM3
Vss
SDRAM4
SDRAM5
Vddq3
SDRAM6
SDRAM7
Vdd
BLOCK DIAGRAM
Buffers
Xin
Xout
REF
OSC
Vddq2
IOAPIC
Buffer
Vddq2
4
PWR_DWN#
Buffers
Vddq3
8
Buffers
6
Buffers
PCICLK_F
Buffer
Vddq4
Buffer
48MHZ
PLL2
Buffer
24MHZ
SDRAM0~7
PCICLK0~5
CPUCLK0~3
3
REF0,1,2
PCICLK0
Vss
PCICLK1
PCICLK2
PCICLK3
PCICLK4
Vddq4
PCICLK5
Vss
SEL0
SEL1
N/C
Vddq4
48MHZ
24MHZ
Vss
SEL0,1
PLL1
dly
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.2
4/24/97
Page 1 of 6
SC652
Clock Generator for Pentium Based Designs W/2 DIMM Support
Approved Product
PIN DESCRIPTION
Xin, Xout
- These pins form an on-chip reference
oscillator when connected to terminals of an external
parallel resonant crystal (nominally 14.318 MHz). Xin
may also serve as input for an externally generated
reference signal.
48MHz
- Frequency output for USB.
SEL(0:1)
- Standard frequency select inputs. They have
internal pull-ups.
CPUCLK(0:3)
- Low skew (<250 pS) clock outputs for
host frequencies such as CPU, Chipset, Cache. Vddq2
is the supply voltage for these outputs.
SDRAM(0:7)
- Synchronous DRAM DIMs clocks. They
are powered by Vddq3.
Vdd
- Power supply pins for analog circuit and core
PCICLK(0:5)
- Low skew (<250pS) clock outputs for
PCI frequencies.
controlled by Vddq3.
PCICLK_F -
A PCI clock output that does not stop until
in power down mode. It is synchronous with other PCI
clocks.
N/C
- No connection pins.
These buffers voltage level is
Vddq3
- Power supply pins for 3.3V IO pins.
Vddq2
- Power supply pins for 2.5V/3.3V IO pins.
logic.
PWR_DWN# -
Power down pin to turn the power of the
whole chip down including the VCOs and the PCICLK_F
output pin. It has an internal pull-up
Vss
- Ground pins for the chip.
24MHz
- Frequency output for super I/O.
IOAPIC
-
Buffered
output
of
14.3MHZ
for
multiprocessor support. It is powered by Vddq2.
REF(0:2)
- Buffered outputs of reference 14.3MHZ.
POWER MANAGEMENT FUNCTIONS
The IMISC652 clocks may be disabled using the PWR_DWN# pin in order to reduce power consumption. All clocks are
stopped in the low state. All clocks maintain a valid high period on transitions from running to stopped. When powered
down, the reference oscillator and VCOs are stopped. On low to high transitions of PWR_DWN#, external circuitry
should allow 3 mS for the VCOs to stabilize prior to assuming the pulse widths are correct.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.2
4/24/97
Page 2 of 6
SC652
Clock Generator for Pentium Based Designs W/2 DIMM Support
Approved Product
MAXIMUM RATINGS
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
Voltage Relative to VSS:
Voltage Relative to VDD:
Storage Temperature:
Ambient Temperature:
Maximum Power Supply:
-0.3V
0.3V
-65ºC to + 150ºC
-55ºC to +125ºC
7V
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
VSS<(Vin or Vout)<VDD
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
ELECTRICAL CHARACTERISTICS
Characteristic
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Output Low Current
Output High Current
Output Low Current
Output High Current
Tri-State leakage Current
Dynamic Supply Current
Static Supply Current
Short Circuit Current
Symbol
VIL
VIH
IIL
IIH
IOL1
IOH1
IOL2
IOH2
Ioz
Idd
Idd
ISC
61
61
42
40
-
-
-
25
-
-
-
-
-
40
200
-
Min
-
2.0
Typ
-
-
Max
0.8
-
-66
5
-
-
-
-
10
-
-
-
Units
Vdc
Vdc
µA
µA
mA
mA
mA
mA
µA
mA
µA
mA
CPU = 66.6 Mhz, No Load
PWR_DWN# = Low
1 output at a time - 30 seconds
VOL1 = 1.6V (@ CPU, SDRAM, PCI,
IOAPIC and REF0 clocks)
VOH1 = 1.0V (@ CPU, SDRAM, PCI,
IOAPIC and REF0 clocks)
VOL2 = 1.9V (@ 48Mhz, 24 Mhz, REF2
and REF1 clocks)
VOH2 = 1.0V (@ 48Mhz, 24 Mhz, REF2
and REF1 clocks)
Conditions
-
-
VDD = VDDq2 = VDDq3 = 3.3V+5%, TA = 0ºC to +70ºC
Contact IMI for IBIS models.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.2
4/24/97
Page 3 of 6
SC652
Clock Generator for Pentium Based Designs W/2 DIMM Support
Approved Product
SWITCHING CHARACTERISTICS
Characteristic
Output Rise (0.4V - 2.0V)
and Fall (2.0V-0.4V) time
Output Duty Cycle
CPU/SDRAM to PCI Offset
Skew (CPU-CPU), (PCI-
PCI), (SDRAM-SDRAM)
Skew (CPU-SDRAM)
∆Period
Cycles, CPU
Jitter Absolute, CPU
Overshoot/Undershoot
Beyond Power Rails
Ring Back Exclusion
Symbol
tTLH,
tTHL
-
tOFF
tSKEW1
tSKEW2
∆P
tjab
V
over
V
RBE
Min
-
45
1
-
-
-
-
-
0.7
-
Typ
-
50
-
-
-
-
Max
1.6
55
4
250
500
+250
500
1.5
2.1
Units
ns
%
ns
ps
ps
ps
ps
V
V
Conditions
22 pf Load
CPU and PCI outputs
Measured at 1.5V
15 pf Load Measured at 1.5V
15 pf Load Measured at 1.5V
15 pf Load Measured at 1.5V
-
-
22 ohms @ source of 8 inch PCB run
to 15 pf load
note1
VDD = VDDq2 = VDDq3 = 3.3V+5%, TA = 0ºC to +70ºC
note 1: Ring Back must not enter this range.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.2
4/24/97
Page 4 of 6
SC652
Clock Generator for Pentium Based Designs W/2 DIMM Support
Approved Product
PCB LAYOUT RECOMMENDATION
Via to VDD Island
Via to GND plane
Via to VCC plane
VCC
1
FB1
1
2
3
IMISC652
C12
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
C3
10µF
4
5
6
7
C11
FB2
VCC
2
C10
C13
10µF
C4
8
9
10
11
12
13
14
15
C9
C5
C6
16
17
18
19
20
21
22
23
24
C8
C7
This is only a layout recommendation for best performance and lower EMI. The designer may choose a
differnent approach but C4, C5, C6, C7, C8, C9, C10, C11and C12 (all are 0.1µf) should always be used and
placed close to their VDD pins.
PACKAGE DRAWING AND DIMENSIONS
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.2
4/24/97
Page 5 of 6
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