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PO100HSTL32A

Description
Quad Differential LVDS/LVPECL/HSTL to LVTTL Translator
File Size493KB,5 Pages
ManufacturerPotato Semiconductor Corporation
Websitehttp://www.potatosemi.com/
Download Datasheet View All

PO100HSTL32A Overview

Quad Differential LVDS/LVPECL/HSTL to LVTTL Translator

PO100HSTL32A
Quad Differential LVDS/LVPECL/HSTL to LVTTL Translator
04/19/09
FEATURES:
Patented Technology
Differential LVDS/LVPECL/HSTL to LVTTL
Translator
Operating frequency up to 1GHz with 2pf load
Operating frequency up to 800MHz with 5pf load
Operating frequency up to 450MHz with 15pf load
Very low output pin to pin skew < 150ps
Propagation delay < 1.8ns max with 15pf load
2.4V to 3.6V power supply
Industrial temperature range: –40°C to 85°C
Available in 16-pin SOIC 150ml package
DESCRIPTION:
Potato Semiconductor’s PO100HSTL32A is
designed for world top performance using
submicron CMOS technology to achieve 1GHz
LVTTL output frequency with less than 1.8ns
propagation delay.
The
PO100HSTL32A
is a low-skew, The small
outline 16 pin package and the low skew design to
make it ideal for applica- tions which require the
translation of a clock or a data signal.
Pin Configuration
1B
1A
1Y
G
2Y
2A
2B
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Logic Block Diagram
V
CC
4B
4A
4Y
G
3Y
3A
3B
G
G
1A
1B
2A
4
12
2
1
6
7
10
9
14
15
13
3
1Y
5
2Y
Pin Description
DIFFERENTIAL INPUT
A, B
V
ID
10 mV
–10 mV < V
ID
< 10 mV
V
ID
–10 mV
X
Open
ENABLES
G
H
X
H
X
H
X
L
H
X
G
X
L
X
L
X
L
H
X
L
OUTPUT
Y
H
H
?
?
L
L
Z
H
H
2B
3A
3B
4A
4B
11
3Y
4Y
1
Copyright
© Potato Semiconductor Corporation
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