or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1
DS1026_14.1
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA Family Overview
The ispXPGA family of devices provides the ideal vehicle for the creation of high-performance logic designs that
are both non-volatile and infinitely re-programmable. Other FPGA solutions force a compromise, being either re-
programmable or non-volatile. This family couples this capability with a mainstream architecture containing the fea-
tures required for today’s system-level design.
The ispXPGA family is available in two options. The standard device supports sysHSI capability for ultra fast serial
communications while the lower-cost “E-Series” supports the same high-performance FPGA fabric without the
sysHSI Block.
Electrically Erasable CMOS (E
2
CMOS) memory cells provide the ispXPGA family with non-volatile capability.
These allow logic to be functional microseconds after power is applied, allowing easy interfacing in many applica-
tions. This capability also means that expensive external configuration memories are not required and that designs
can be secured from unauthorized read back. Internal SRAM cells allow the device to be infinitely reconfigured if
desired. Both the SRAM and E
2
CMOS cells can be programmed and verified through the IEEE 1532 industry stan-
dard. Additionally, the SRAM cells can be configured and read-back through the sysCONFIG™ peripheral port.
The family spans the density and I/O range required for the majority of today’s logic designs, 139K to 1.25M system
gates and 160 to 496 I/O. The devices are available for operation from 1.8V, 2.5V, and 3.3V power supplies, provid-
ing easy integration into the overall system.
System-level design needs are met through the incorporation of sysMEM dual-port memory blocks, sysIO
advanced I/O support, and sysCLOCK Phase Locked Loops (PLLs). High-speed serial communications are sup-
ported through multiple sysHSI blocks, which provide clock data recovery (CDR) and serialization/de-serialization
(SERDES).
The ispLEVER™ design tool from Lattice allows easy implementation of designs using the ispXPGA product. Syn-
thesis library support is available for major logic synthesis tools. The ispLEVER tool takes the output from these
common synthesis packages and place and routes the design in the ispXPGA product. The tool supports floor
planning and the management of other constraints within the device. The tool also provides outputs to common
timing analysis tools for timing analysis.
To increase designer productivity, Lattice provides a variety of pre-designed modules referred to as IP cores for the
ispXPGA product. These IP cores allow designers to concentrate on the unique portions of their design while using
pre-designed blocks to implement standard functions such as bus interfaces, standard communication interfaces,
and memory controllers.
Through the use of advanced technology and innovative architecture the ispXPGA FPGA devices provide design-
ers with excellent speed performance. Although design dependent, many typical designs can run at over 150MHz.
Certain designs can run at over 300MHz. Table 2 details the performance of several building blocks commonly
used by logic designers.
Table 2. ispXPGA Speed Performance for Typical Building Blocks
Function
8:1 Asynch MUX
1:32 Asynch Demultiplexer
8 x 8 2-LL Pipelined Multiplier
32-bit Up/Down Counter
32-bit Shift Register
Performance
150 MHz
125 MHz
225 MHz
290 MHz
360 MHz
2
Lattice Semiconductor
ispXPGA Family Data Sheet
Architecture Overview
The ispXPGA architecture is a symmetrical architecture consisting of an array of Programmable Function Units
(PFUs) enclosed by Input Output Groups (PICs) with columns of sysMEM Embedded Block RAMs (EBRs) distrib-
uted throughout the array. Figure 1 illustrates the ispXPGA architecture. Each PIC has two corresponding sysIO
blocks, each of which includes one input and output buffer. On two sides of the device, between the PICs and the
sysIO blocks, there are sysHSI High-Speed Interface blocks. The symmetrical architecture allows designers to eas-
ily implement their designs, since any logic function can be placed in any section of the device.
The PFUs contain the basic building blocks to create logic, memory, arithmetic, and register functions. They are
optimized for speed and flexibility allowing complex designs to be implemented quickly and efficiently.
The PICs interface the PFUs and EBRs to the external pins of the device. They allow the signals to be registered
quickly to minimize setup times for high-speed designs. They also allow connections directly to the different logic
elements for fast access to combinatorial functions.
The sysMEM EBRs are large, fast memory elements that can be configured as RAM, ROM, FIFO, and other stor-
age types. They are designed to facilitate both single and dual-port memory for high-speed applications.
These three components of the architecture are interconnected via a high-speed, flexible routing array. The routing
array consists of Variable Length Interconnect (VLI) lines between the PICs, PFUs, and EBRs. There is additional
routing available to the PFU for feedback and direct routing of signals to adjacent PFUs or PICs.
The sysIO blocks consist of configurable input and output buffers connected directly to the PICs. These buffers can
be configured to interface with 16 different I/O standards. This allows the ispXPGA to interface with other devices
without the need for external transceivers.
The sysHSI blocks provide the necessary components to allow the ispXPGA device to transfer data at up to
800Mbps using the LVDS standard. These components include serializing, de-serializing, and clock data recovery
(CDR) logic.
The sysCLOCK blocks provide clock multiplication/division, clock distribution, delay compensation, and increased
performance through the use of PLL circuitry that manipulates the global clocks. There is one sysCLOCK block for
each global clock tree in the device.
3
Lattice Semiconductor
Figure 1. ispXPGA Block Diagram
ispXPGA Family Data Sheet
PFU
PIC
sysMEM Block
sysCLOCK PLL
sysHSI Block
sysIO Buffer
Programmable Function Unit
The Programmable Function Unit (PFU) is the basic building block of the ispXPGA architecture. The PFUs are
arranged in rows and columns in the device with PFU (1,1) referring to (row 1, column 1). Each PFU consists of
four Configurable Logic Elements (CLEs), four Configurable Sequential Elements (CSEs), and a Wide Logic Gen-
erator (WLG). By utilizing these components, the PFU can implement a variety of functions. Table 3 lists some of
the function capabilities of the PFU.
There are 57 inputs to each PFU and nine outputs. The PFU uses 20 inputs for logic, and 37 inputs drive the con-
trol logic from which six control signals are derived for the PFU.
Table 3. Function Capability of ispXPGA PFU
Function
Look-up table
Wide logic functions
Multiplexing
Arithmetic logic
Single-port RAM
Double-port RAM
Shift register
LUT-4, LUT-5, LUT-6
Up to 20 input logic functions
2:1, 4:1, 8:1
Dedicated carry chain and booth multiplication logic
16X1, 16X2, 16X4, 32X1, 32X2, 64X1
16X1, 16X2, 32X1
8-bit shift registers (up to 32-bit shift capability)
I want to transplant the MFC program developed in WINCE5.0 to WINCE6.0, but I can't succeed. I'd like to ask for your advice: My current environment is VS2005+WINCE6.0. I searched online before and fo...
Haha, isn't it said that everyone should show off their prizes? Why hasn't anyone done so? Show them off and let everyone congratulate you.
Don't be so low-key ;P...
I am currently working on an algorithm implementation. I originally used an iterative structure to implement it. When I wanted to increase the speed and use a pipeline structure to implement it, I fou...
[align=left][b][size=10.5pt][/size][/b][/align] [align=left][b][size=10.5pt][font=Times New Roman][font=新宋体][size=4][color=royalblue]1[/color][size=10.5pt][color=royalblue].[/color][/size][/size][/fon...
No one paid attention to the official website consultation. The official QQ group consultation people told me to look up the information and solve it myself. Why would I ask you when I can look up the...
In the latest update, the code size of neopixel was reduced and the fill() speed was optimized.drivers/neopixel: Reduce code size of driver.
drivers/neopixel: Optimize fill() for speed....
As a wireless broadband metropolitan area network standard, WiMAX technology has greater advantages than previous 3.5GHz MMDS products in terms of non-line-of-sight transmission and spectrum utiliz...[Details]
1. Introduction
This design was made for participating in an electronic design competition. It effectively solved the problem of the operation and control of an electric car on a seesaw. The s...[Details]
Do you often have to add brake fluid to your car's brakes? The fact that you need to pump out the brake fluid to make sure there is no gas in the brake fluid line may not be done by the car owner h...[Details]
With the advent of increasingly powerful processors, image sensors, memory, and other semiconductor devices, as well as the algorithms that enable them, computer vision can be implemented in a wide...[Details]
introduction
In the discharge process of tokamak plasma physics, the study of rupture and sawtooth is of great significance. Rupture and sawtooth exist in most tokamaks. Rupture is a notew...[Details]
For a long time, due to the limitation of hardware conditions, the display devices of traditional small handheld devices such as PDA are usually monochrome LCD, and the user interface is very simpl...[Details]
12v Lead Acid batteries used in trucks, cars, RVs and uninterruptible power supplies are usually rated at 12V. This circuit monitors the battery, the charge and discharge curves, gives the cu...[Details]
Investment in
the
medical device
industry has been on the rise in recent years. In the past two years, venture capital for medical devices has almost doubled, reaching $4 billion in 2007. Fr...[Details]
As people's requirements for safety and comfort in the process of driving cars continue to increase, automotive radars are widely used in the car's adaptive cruise system, collision avoidance syste...[Details]
Motors are important products that convert electrical energy into mechanical energy to achieve automation, and they are widely used in industrial control, medical electronics, white a...[Details]
Abstract: With the development and construction of BeiDou II system, China will shift from the situation dominated by GPS to the situation dominated by BeiDou II global navigation system independen...[Details]
hint:
The number of speakers and their spacing limit the sound field of a portable stereo system.
Spatial audio attempts to artificially recreate the experience of listening to sounds i...[Details]
Recently, news came from the certification department that the photovoltaic grid-connected inverter of Samil New Energy Co., Ltd. (hereinafter referred to as "Samil New Energy") has once again obta...[Details]
1 Basic Features
In computer control systems and various intelligent instruments and meters composed of single-chip microcomputers (or microprocessors), various external analog signals must be ...[Details]
introduction
Steam turbines are driven by high-temperature and high-pressure steam generated by boilers to run at high speed. They are key power equipment in thermal power plants. The emergenc...[Details]
Embedded System
京公网安备 11010802033920号
EEWORLD
