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IDT74ALVC08PY

Description
ALVC/VCX/A SERIES, QUAD 2-INPUT AND GATE, PDSO14
Categorysemiconductor    logic   
File Size53KB,5 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
Download Datasheet Parametric Compare View All

IDT74ALVC08PY Overview

ALVC/VCX/A SERIES, QUAD 2-INPUT AND GATE, PDSO14

IDT74ALVC08PY Parametric

Parameter NameAttribute value
Number of functions4
Number of terminals14
Maximum operating temperature85 Cel
Minimum operating temperature-40 Cel
Maximum supply/operating voltage3.6 V
Minimum supply/operating voltage2.7 V
Rated supply voltage3.3 V
Processing package descriptionTSSOP-14
stateDISCONTINUED
CraftsmanshipCMOS
packaging shapeRectangle
Package SizeSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
surface mountYes
Terminal formGULL WING
Terminal spacing0.6500 mm
terminal coatingtin lead
Terminal locationpair
Packaging MaterialsPlastic/Epoxy
Temperature levelINDUSTRIAL
seriesALVC/VCX/A
Logic IC typeAND
Number of inputs2
propagation delay TPD3.4 ns
IDT74ALVC08
3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-AND GATE
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS QUADRUPLE
2-INPUT POSITIVE-AND GATE
IDT74ALVC08
• 0.5 MICRON CMOS Technology
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• V
CC
= 3.3V ± 0.3V, Normal Range
• V
CC
= 2.7V to 3.6V, Extended Range
• V
CC
= 2.5V ± 0.2V
• CMOS power levels (0.4µ W typ. static)
µ
• Rail-to-Rail output swing for increased noise margin
• Available in SOIC, SSOP, and TSSOP packages
FEATURES:
DESCRIPTION:
This quadruple 2-input positive-AND gate is built using advanced dual
metal CMOS technology. The ALVC08 performs the Boolean function Y =
A • B or Y =
A
+
B
in positive logic.
The ALVC08 has been designed with a ±24mA output driver. This driver
is capable of driving a moderate to heavy load while maintaining speed
performance.
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Suitable for Heavy Loads
APPLICATIONS:
• 3.3V high speed systems
• 3.3V and lower voltage computing systems
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
1
A
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
4
B
4
A
4
Y
3
B
3
A
3
Y
A
Y
B
1
B
1
Y
2
A
2
B
2
Y
GND
SOIC/ SSOP/ TSSOP
TOP VIEW
PIN DESCRIPTION
Pin Names
xA, xB
xY
Data Inputs
Data Outputs
Description
FUNCTION TABLE
(EACH GATE)
(1)
Inputs
xA
H
L
X
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Output
xB
H
X
L
xY
H
L
L
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
©2000 Integrated Device Technology, Inc.
SEPTEMBER 2000
DSC-4633/1

IDT74ALVC08PY Related Products

IDT74ALVC08PY IDT74ALVC08 IDT74ALVC08DC IDT74ALVC08PG
Description ALVC/VCX/A SERIES, QUAD 2-INPUT AND GATE, PDSO14 ALVC/VCX/A SERIES, QUAD 2-INPUT AND GATE, PDSO14 ALVC/VCX/A SERIES, QUAD 2-INPUT AND GATE, PDSO14 ALVC/VCX/A SERIES, QUAD 2-INPUT AND GATE, PDSO14
Number of functions 4 4 4 4
Number of terminals 14 14 14 14
Maximum operating temperature 85 Cel 85 Cel 85 Cel 85 Cel
Minimum operating temperature -40 Cel -40 Cel -40 Cel -40 Cel
Maximum supply/operating voltage 3.6 V 3.6 V 3.6 V 3.6 V
Minimum supply/operating voltage 2.7 V 2.7 V 2.7 V 2.7 V
Rated supply voltage 3.3 V 3.3 V 3.3 V 3.3 V
Processing package description TSSOP-14 TSSOP-14 TSSOP-14 TSSOP-14
state DISCONTINUED DISCONTINUED DISCONTINUED DISCONTINUED
Craftsmanship CMOS CMOS CMOS CMOS
packaging shape Rectangle Rectangle Rectangle Rectangle
Package Size SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
surface mount Yes Yes Yes Yes
Terminal form GULL WING GULL WING GULL WING GULL WING
Terminal spacing 0.6500 mm 0.6500 mm 0.6500 mm 0.6500 mm
terminal coating tin lead tin lead tin lead tin lead
Terminal location pair pair pair pair
Packaging Materials Plastic/Epoxy Plastic/Epoxy Plastic/Epoxy Plastic/Epoxy
Temperature level INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL
series ALVC/VCX/A ALVC/VCX/A ALVC/VCX/A ALVC/VCX/A
Logic IC type AND AND AND AND
Number of inputs 2 2 2 2
propagation delay TPD 3.4 ns 3.4 ns 3.4 ns 3.4 ns
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