HANBit
HMNR5128D(V)
5.0 or 3.3V, 4 Mbit (512 Kbit x 8) TIMEKEEPER NVSRAM
Part No. HMNR5128D(V)
GENERAL DESCRIPTION
The HMNR5128D(V) TIMEKEEPER SRAM is a 512Kb x 8 non-volatile static RAM and real time clock organized as
524,280 words by 8 bits. The special DIP package provides a fully integrated battery back-up memory and real time clock
solution. The HMNR5128D(V) directly replaces industry standard 512Kbit x 8 SRAMs. It also provides the non-volatility of
Flash without any requirement for special WRITE timing or limitations on the number of WRITEs that can be performed.
FEATURES
■
INTEGRATED LOW POWER SRAM, REAL TIME CLOCK, POWER-FAIL CONTROL CIRCUIT, BATTERY and
CRYSTAL
■
BCD CODED YEAR, MONTH, DAY, DATE, HOURS, MINUTES, and SECONDS
■
AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION VOLTAGES :
(V
PFD
= Power-fail Deselect Voltage)
–
HMNR5128D : V
CC
= 4.5 to 5.5V
4.2V
≤
V
PFD
≤
4.5V
–
HMNR5128DV: V
CC
= 3.0 to 3.6V
2.7V
≤
V
PFD
≤
3.0V
■
CONVENTIONAL SRAM OPERATION : UNLIMITED WRITE CYCLES
■
SOFTWARE CONTROLLED CLOCK CALIBRATION FOR HIGH ACCURACY APPLICATIONS
■
10 YEARS OF DATA RETENTION and CLOCK OPERATION IN THE ABSENCE OF POWER PIN and FUNCTION
COMPATIBLE WITH INDUSTRY STANDARD 512K x 8 SRAMS
■
SELF-CONTAINED BATTERY and CRYSTAL IN DIP PACKAGE
OPTIONS
w
Timing
70 ns
85 ns
MARKING
-70
-85
PIN ASSIGNMENT
A
18
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
0
DQ
1
DQ
2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A
15
A
17
/WE
A
13
A
8
A
9
A
11
/OE
A
10
/CE
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
32-pin Encapsulated Package
URL : www.hbe.co.kr
Rev. 2.0 (March, 2002)
1
HANBit Electronics Co.,Ltd
HANBit
FUNCTIONAL DESCRIPTION
HMNR5128D(V)
The HMNR5128D(V) is a full function, year 2000 compliant (Y2KC), real– time clock/calendar (RTC) and 512k x 8 non-
volatile static RAM. User access to all registers within the HMNR5128D(V) is accomplished with a bytewide interface . The
Real-time clock (RTC) information and control bits reside in the eight upper most RAM locations. The RTC registers
contain century, year, month, date, day, hours, minutes, and seconds data in 24-hour BCD format. Corrections for the date
of each month and leap year are made automatically. The RTC clock registers are double buffered to avoid access of
incorrect data that can occur during clock update cycles. The double buffered system also prevents time loss as the
timekeeping countdown continues unabated by access to time register data. The HMNR5128D(V) also contains its own
power-fail circuitry which deselects the device when the V
CC
supply is in an out of tolerance condition. This feature
prevents loss of data from unpredictable system operation brought on by low V
CC
as errant access and update cycles are
avoided.
BLOCK DIAGRAM
OSCILLATOR AND
CLOCK CHAIN
32.768KHz
CRYSTAL
16 x 8
TIMEKEEPER
REGISTER
A0 ~ A18
POWER
524,272 x 8
SRAM ARRAY
V
PFD
VOLTAGE SENSE
AND
SWITCHING
CIRCURITY
LITHIUM
CELL
DQ0 ~ DQ7
/CE
/WE
/OE
Vcc
A0-A18 : Address Input
/CE : Chip Enable
V
ss
: Ground
DQ0-DQ7 : Data In / Data Out
/WE : Write Enable
/OE : Output Enable
V
CC
: Power (+5V or +3.3V)
NC : No Connection
Vss
URL : www.hbe.co.kr
Rev. 2.0 (March, 2002)
2
HANBit Electronics Co.,Ltd
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Absolute Maximum Ratings
Symbol
T
A
T
STG
T
SLD
(1)
HMNR5128D(V)
Parameter
AmbientOperatingTemperature
Storage Temperature(Vcc Off, Oscillator Off)
Lead Solder Temperature for 10 seconds
Input or Output Voltage
Supply Voltage
Output Current
Power Dissipation
HMNR5128D
HMNR5128DV
Value
0 to 70
-40 to 70
260
-0.3 to Vcc+0.3
4.5 to 5.5
3.0 to 3.6
20
1
Unit
°
C
°
C
°
C
V
V
V
mA
W
V
IO
V
CC
I
O
P
D
Note
: Permanent device damage may occur if Absolute Maximum Ratings are exceeded.
Functional operation should be restricted to the Recommended DC Operating Conditions detailed in this data sheet.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
(1) Soldering temperature not to exceed 260° C for 10 seconds (Total thermal budget not to exceed 150° C for longer
than 30 seconds).
Caution
: Negative undershoots below
–
0.3V are not allowed on any pin while in the Battery Back-up mode.
Operating and AC Measurement Conditions
Parameter
V
CC
Supply Voltage
Ambient Operating Temperature
Load Capacitance (C
L
)
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref. Voltages
HMNR5128D
4.5 to 5.5
0 to 70
100
≤
5
0 to 3
1.5
HMNR5128DV
3.0 to 3.6
0 to 70
50
≤
5
0 to 3
1.5
Unit
V
°
C
pS
nS
V
V
AC Measurement Load Circuit
Note
: 50pF for HMNR5128DV
URL : www.hbe.co.kr
Rev. 2.0 (March, 2002)
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HANBit Electronics Co.,Ltd
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Capacitance
Symbol
C
IN
C
OUT
Note
:
1.
2.
3.
(3)
HMNR5128D(V)
Parameter
(1,2)
Min
Max
10
10
Unit
pF
pF
Input Capacitance
Input/Output Capacitance
Effective capacitance measured with power supply at 5V (HMNR5128D) or 3.3V (HMNR5128DV). Sampled only,
not 100% tested.
At 25° C, f = 1MHz.
Outputs deselected.
DC Characteristics
Symbol
I
LI
I
LO
(2)
Parameter
Input Leakage Current
Output Leakage Current
Supply Current
Supply Current (Standby) TTL
Supply Current (Standby)
CMOS
Battery Current OSC ON
Test Condition
0V
≤
V
IN
≤
V
CC
0V
≤
V
OUT
≤
V
CC
Outputs open
/CE=V
IH
/CE=V
CC
-0.2
(1)
HMNR5128D
Min
Typ
Max
±
1
±
1
8
15
5
3
575
100
-0.3
2.2
0.8
VCC+
0.3
0.4
0.4
2.4
2.0
3.6
100
100
4.1
4.35
4.5
2.7
2.4
2.0
800
HMN5128DV
Min
Typ
Max
±
1
±
1
4
10
3
2
575
800
100
-0.3
2.0
0.8
VCC+
0.3
0.4
0.4
Unit
uA
uA
mA
mA
mA
nA
nA
V
V
V
V
V
I
CC
I
CC1
I
CC2
I
BAT
V
IL
V
IH
Battery Current OSC
OFF
Input Low Voltage
Input High Voltage
Output Low Voltage
I
OL
=2.1mA
I
OL
=10mA
I
OH
=-1.0mA
I
OUT2
=-1.0uA
V
OUT1
> V
CC
-0.3
V
OUT2
>V
BAT
-0.3
V
OL
V
OH
V
OHB
I
OUT1
I
OUT2
V
PFD
V
SO
V
BAT
Output Low Voltage
(open drain)
(4)
Output High Voltage
V
OH
Battery Back-up
V
OUT
Current (Active)
V
OUT
Current (Battery Back-up)
Power-fail Deselect Voltage
Battery Back-up Switchover
Voltage
Battery Voltage
3.6
70
100
2.9
V
PFD
-
3.0
V
mA
uA
V
V
V
3.0
100
mV
3.0
3.0
Note:
1. Valid for Ambient Operating Temperature: TA =0 to 70° C or 40 to 85° ;
C
VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
2. Outputs deselected.
URL : www.hbe.co.kr
Rev. 2.0 (March, 2002)
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HANBit Electronics Co.,Ltd
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OPERATING MODES
HMNR5128D(V)
The 32-pin, 600mil DIP Hybrid houses a controller chip, SRAM, quartz crystal, and a long life lithium button cell in a single
package. The clock locations contain the year, month, date, day, hour, minute, and second in 24 hour BCD format.
Corrections for 28, 29 (leap year-compliant until the year 2100), 30, and 31 day months are made automatically. Byte
7FFF8h is the clock control register. This byte controls user access to the clock information and also stores the clock
calibration setting. The seven clock bytes (7FFFFh-7FFF9h) are not the actual clock counters, they are memory locations
consisting of READ/WRITE memory cells within the static RAM array. The HMNR5128D(V) includes a clock control circuit
which updates the clock bytes with current information once per second. The information can be accessed by the user in
the same manner as any other location in the static memory array. The HMNR5128D(V) also has its own Power-Fail
Detect circuit. This control circuitry constantly monitors the supply voltage for an out of tolerance condition.
When V
CC
is out of tolerance, the circuit write protects the TIMEKEEPER register data and SRAM, providing data security
in the midst of unpredictable system operation. As V
CC
falls, the control circuitry automatically switches to the battery,
maintaining data and clock operation until valid power is restored.
Operating Modes
Mode
Deselect
WRITE
READ
READ
Deselect
Deselect
VCC
4.5V to 5.5V
or
3.0V to 3.6V
V
SO
to V
PFD
(min)
≤
V
SO
(1)
/CE
VIH
VIL
VIL
VIL
X
X
/OE
X
X
VIL
VIH
X
X
/WE
X
VIL
VIH
VIH
X
X
DQ7
–
DQ0
High-Z
DIN
DOUT
High
High
High
Power
Standby
Active
Active
Active
CMOS
Standby
Battery Back-
up
Note : X = V
IH
or V
IL
; V
SO
= Battery Back-up Switchover Voltage.
READ Mode
The HMNR5128D(V) is in the READ Mode whenever /WE (WRITE Enable) is high and /CE (Chip Enable) is low. The
unique address specified by the 15 Address Inputs defines which one of the 32,768 bytes of data is to be accessed. Valid
data will be available at the Data I/O pins within Address Access Time (t
AVQV
) after the last address input signal is stable,
providing the /CE and /OE access times are also satisfied. If the /CE and /OE access times are not met, valid data will be
available after the latter of the Chip Enable Access Times (t
ELQV
) or Output Enable Access Time (t
GLQV
). The state of the
eight three-state Data I/O signals is controlled by /CE and /OE. If the outputs are activated before t
AVQV
, the data lines will
be driven to an indeterminate state until t
AVQV
. If the Address Inputs are changed while /CE and /OE remain active, output
data will remain valid for Output Data Hold Time (t
AXQX
) but will go indeterminate until the next Address Access.
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Rev. 2.0 (March, 2002)
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HANBit Electronics Co.,Ltd
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