581
1
BiMOS II 12-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
Designed primarily for use with vacuum-fluorescent displays, the
UCN5811A smart power BiMOS II driver features low-output saturation
voltages and high output switching speed. These devices contain CMOS shift
registers, data latches, and control circuitry, and bipolar high-speed sourcing
outputs with DMOS active pull-down circuitry. The high-speed shift register
and data latches allow direct interface with microprocessor-based systems. A
CMOS serial data output enables cascade connections in applications requir-
ing additional drive lines.
The UCN5811A features 60 V and -40 mA output ratings, allowing it to
be used in many other peripheral power driver applications. It can be used as
an improved replacement tor the SN75512B. The Allegro devices do not
require special power-up sequencing.
The UCN5811A has been designed with BiMOS II logic for improved
data entry rates. With a 5 V supply, it will operate to at least 3.3 MHz. At
12 V, higher speeds are possible. Use of this device with TTL may require
the use of appropriate pull-up resistors to ensure a proper input logic high.
This device is supplied in a 20-pin plastic dual in-line package. It can be
operated over the ambient temperature range of -20°C to +85°C. Copper lead
frames and low output saturation voltages allow all outputs to be operated at
25 mA continuously at ambient temperatures of up to 76°C.
Data Sheet
26182.20B
OUT
11
OUT
12
BLANKING
SERIAL
DATA OUT
SERIAL
DATA IN
LOGIC
SUPPLY
CLOCK
STROBE
OUT
1
OUT
2
1
2
3
4
BLNK
20
19
18
17
OUT
10
OUT
9
OUT
8
OUT
7
LOAD
SUPPLY
GROUND
OUT
6
OUT
5
OUT
4
OUT
3
REGISTER
LATCHES
5
6
7
8
9
10
V
DD
CLK
ST
V
BB
16
15
14
13
12
11
Dwg. PP-029-5
FEATURES
ABSOLUTE MAXIMUM RATINGS
at
T
A
= 25
°
C
Logic Supply Voltage,V
DD
..................... 15 V
Driver Supply Voltage, V
BB
................... 60 V
Continuous Output Current,
I
OUT
......................... -40 mA to +25 mA
Input Voltage Range,
V
IN
....................... -0.3 V to V
DD
+ 0.3 V
Package Power Dissipation,
P
D
........................................ See Graph
Operating Temperature Range,
T
A
................................. -20
°
C to +85
°
C
Storage Temperature Range,
T
S
............................... -55
°
C to +150
°
C
I
I
I
I
I
I
To 3.3 MHz Data Input Rate
Low-Power CMOS Logic and Latches
High-Speed Source Drivers
Active Pull-Downs
Low-Output Saturation Voltages
Improved Replacement for SN75512B
Always order by complete part number:
UCN5811A
.
5811
BiMOS II 12-BIT
SERIAL-INPUT,
LATCHED SOURCE DRIVERS
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
2.5
FUNCTIONAL BLOCK DIAGRAM
CLOCK
SERIAL
DATA IN
V
DD
LOGIC
SUPPLY
SERIAL
DATA OUT
2.0
SERIAL-PARALLEL SHIFT REGISTER
1.5
R
θ
J
A
=
55
°
C
/W
STROBE
LATCHES
1.0
BLANKING
MOS
BIPOLAR
0.5
V
BB
LOAD
SUPPLY
0
25
50
75
100
125
AMBIENT TEMPERATURE IN
°C
150
Dwg. GS-004-1
GROUND
OUT
1
OUT
2
OUT
3
OUT
N
Dwg. FP-013-1
TYPICAL INPUT CIRCUIT
VDD
IN
TIMING WAVESHAPES
Dwg. EP-010-5
TYPICAL OUTPUT DRIVER
Dwg. W-184
Dwg. W-182
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 1985, 2000 Allegro MicroSystems, Inc.
5811
BiMOS II 12-BIT
SERIAL-INPUT,
LATCHED SOURCE DRIVERS
ELECTRICAL CHARACTERISTICS at T
A
= +25
°
C, V
BB
= 60 V (unless otherwise noted).
Limits @ V
DD
= 5 V
Characteristic
Output Leakage Current
Output Voltage
Symbol
I
CEX
V
OUT(H)
V
OUT(L)
Test Conditions
V
OUT
= 0 V, T
A
= +70°C
I
OUT
= -25 mA, V
BB
= 60 V
I
OUT
= 1 mA
I
OUT
= 2 mA
Output Pull-Down Current
I
OUT(L)
V
OUT
= 10 V to V
BB
V
OUT
= 40 V to V
BB
Input Voltage
V
IN(1)
V
IN(0)
Input Current
I
IN(1)
I
IN(0)
Serial Data Output Voltage
V
OUT(H)
V
OUT(L)
Maximum Clock Frequency
Supply Current
f
clk
I
DD(H)
I
DD(L)
I
BB(H)
I
BB(L)
Blanking to Output Delay
t
PHL
t
PLH
Output Fall Time
Output Rise Time
t
f
t
r
All Outputs High
All Outputs Low
Outputs High, No Load
Outputs Low
C
L
= 30 pF
C
L
= 30 pF
C
L
= 30 pF
C
L
= 30 pF
V
IN
= V
DD
V
IN
= 0.8 V
I
OUT
= -200
µA
I
OUT
= 200
µA
Mln.
—
58
—
—
2.5
—
3.5
-0.3
—
—
4.5
—
3.3*
—
—
—
—
—
—
—
—
Typ.
-5.0
58.5
2.0
—
4.0
—
—
—
0.05
-0.05
4.7
200
—
3.0
2.5
7.5
10
300
250
1000
150
Max.
-15
—
3.0
—
—
—
5.3
+0.8
0.5
-0.5
—
250
—
5.0
4.0
12
100
550
450
1250
170
Limits @ V
DD
= 12 V
Min.
—
58
—
—
—
15
10.5
-0.3
—
—
11.7
—
—
—
—
—
—
—
—
—
—
Typ.
-5.0
58.5
—
2.0
—
18
—
—
0.1
-1.0
11.8
100
—
15
7.0
7.5
10
125
170
250
150
Max.
-15
—
—
3.0
—
—
12.3
+0.8
1.0
-1.0
—
200
—
20
10
12
100
150
200
300
170
Units
µA
V
V
V
mA
mA
V
V
µA
µA
V
mV
MHz
mA
mA
mA
µA
ns
ns
ns
ns
Negative current is defined as coming out of (sourcing) the specified device pin.
* Operation at a clock frequency greater than the specified minimum value is possible but not warranteed.
www.allegromicro.com
5811
BiMOS II 12-BIT
SERIAL-INPUT,
LATCHED SOURCE DRIVERS
CLOCK
DATA IN
C
STROBE
BLANKING
G
OUT
N
Dwg. No. 12,649A
A
B
D
E
F
Serial Data present at the input is transferred
to the shift register on the logic “0” to logic “1”
transition of the CLOCK input pulse. On
succeeding CLOCK pulses, the registers shift data
information towards the SERIAL DATA OUT-
PUT. The SERIAL DATA must appear at the
input prior to the rising edge of the CLOCK input
waveform.
Information present at any register is trans-
ferred to the respective latch when the STROBE
is high (serial-to-parallel conversion). The
latches will continue to accept new data as long as
the STROBE is held high. Applications where
the latches are bypassed (STROBE tied high) will
require that the BLANKING input be high during
serial data entry.
When the BLANKING input is high, the
output source drivers are disabled (OFF); the
DMOS sink drivers are ON, the information
stored in the latches is not affected by the
BLANKING input. With the BLANKING input
low, the outputs are controlled by the state of
their respective latches.
TIMING REQUIREMENTS
(T
A
= +25°C,V
DD
= 5 V, Logic Levels are V
DD
and Ground)
A.
Minimum Data Active Time Before Clock Pulse
(Data Set-Up Time) ..........................................................................
75 ns
B.
Minimum Data Active Time After Clock Pulse
(Data Hold Time) .............................................................................
75 ns
C.
Minimum Data Pulse Width ................................................................
150 ns
D.
Minimum Clock Pulse Width ...............................................................
150 ns
E.
Minimum Time Between Clock Activation and Strobe .......................
300 ns
F.
Minimum Strobe Pulse Width .............................................................
100 ns
G.
Typical Time Between Strobe Activation and
Output Transistion .........................................................................
500 ns
Timing is representative of a 3.3 MHz clock. Higher speeds may be attainable
with increased supply voltage; operation at high temperatures will reduce the
specified maximum clock frequency.
TRUTH TABLE
Serial
Shift Register Contents
Data Clock
Input Input I
1
I
2
I
3
... I
N-1
I
N
H
L
X
H
L
R
1
R
2
...
R
1
R
2
...
R
N-2
R
N-1
R
N-2
R
N-1
R
N-1
R
N
X
X
Serial
Data Strobe
Output Input
R
N-1
R
N-1
R
N
X
P
N
X = Irrelevant
Latch Contents
I
1
I
2
I
3
...
I
N-1
I
N
Blanklng
Output Contents
I
1
I
2
I
3
... I
N-1
I
N
R
1
R
2
R
3
...
X
P
N
X
X
...
L
H
R
1
R
2
R
3
...
P
1
P
2
P
3
...
X X X ...
R
N-1
R
N
P
N-1
P
N
X
X
L
H
P
1
P
2
P
3
... P
N-1
L L L ... L
L
P
1
P
2
P
3
...
L = Low Logic Level
P
N-1
P
N
H = High Logic Level
P = Present State
R = Previous State
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
5811
BiMOS II 12-BIT
SERIAL-INPUT,
LATCHED SOURCE DRIVERS
UCN5811A
Dimensions in Inches
(controlling dimensions)
20
11
0.014
0.008
0.430
0.280
0.240
MAX
0.300
BSC
1
0.070
0.045
0.100
1.060
0.980
BSC
10
0.005
MIN
0.210
MAX
0.015
MIN
0.150
0.115
0.022
0.014
Dwg. MA-001-20 in
NOTES: 1.
2.
3.
4.
Exact body and lead configuration at vendor’s option within limits shown.
Lead spacing tolerance is non-cumulative.
Lead thickness is measured at seating plane or below.
Supplied in standard sticks/tubes of 18 devices.
www.allegromicro.com
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