- 48-lead flatpack, 25 mil pitch (.390 x .640), wgt 1.4 Grams
DESCRIPTION
The 16-bit wide UT54ACS162245SLV MultiPurpose low volt-
age transceiver is built using Aeroflex’s epitaxial CMOS tech-
nology and is ideal for space applications. This high speed, low
power UT54ACS162245SLV low voltage transceiver is de-
signed to perform multiple functions including: asynchronous
two-way communication, Schmitt input buffering, voltage trans-
lation, warm and cold sparing. With V
DD
equal to zero volts, the
UT54ACS162245SLV outputs and inputs present a minimum
impedance of 1MΩ making it ideal for "cold spare" applications.
Balanced outputs and low "on" output impedance make the
UT54ACS162245SLV well suited for driving high capacitance
loads and low impedance backplanes. The
UT54ACS162245SLV enables system designers to interface 2.5
volt CMOS compatible components with 3.3 volt CMOS com-
ponents. For voltage translation, the A port interfaces with the
2.5 volt bus; the B port interfaces with the 3.3 volt bus. The
direction control (DIRx) controls the direction of data flow. The
output enable (OEx) overrides the direction control and disables
both ports. These signals can be driven from either port A or B.
The direction and output enable controls operate these devices
as either two independent 8-bit transceivers or one 16-bit trans-
ceiver.
LOGIC SYMBOL
OE1 (48)
OE2 (25)
(1)
DIR1
(47)
(46)
(44)
G1
G2
2EN1 (BA)
2EN2 (AB)
1EN1 (BA)
1EN2 (AB)
11
12
(24)
DIR2
1A1
1A2
1A3
(2)
(3)
(5)
(6)
(8)
1B1
1B2
1B3
1B4
(43)
1A4
(41)
1A5
(40)
1A6
(38)
1A7
(37)
1A8
(36)
2A1
2A2
2A3
(35)
(33)
21
22
1B5
(9)
1B6
(11)
1B7
(12)
1B8
(13)
2B1
(14)
2B2
(16)
2B3
(17)
2B4
(19)
2B5
(20)
2B6
(22)
2B7
(23)
2B8
(32)
2A4
(30)
2A5
(29)
2A6
(27)
2A7
(26)
2A8
PIN DESCRIPTION
Pin Names
OEx
DIRx
xAx
xBx
Description
Output Enable Input (Active Low)
Direction Control Inputs
Side A Inputs or 3-State Outputs (2.5V Port)
Side B Inputs or 3-State Outputs (3.3V Port)
1
PINOUTS
48-Lead Flatpack
Top View
DIR1
1B1
1B2
V
SS
1B3
1B4
VDD1
1B5
1B6
V
SS
1B7
1B8
2B1
2B2
V
SS
2B3
2B4
VDD1
2B5
2B6
V
SS
2B7
2B8
DIR2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
OE1
1A1
1A2
V
SS
1A3
1A4
VDD2
1A5
1A6
V
SS
1A7
1A8
2A1
2A2
V
SS
2A3
2A4
VDD2
2A5
2A6
V
SS
2A7
2A8
OE2
powered up first to ensure proper control of output enable
(/OEx) and direction control (DIRx). Control of the outputs /
OEx and DIRx pins is not guaranteed until V
DD2
reaches 1.5 +/
-5%. During normal operation of the device, after power up,
insure V
DD1
≥V
DD2
.
Power Up Sequence
Users should power up V
DD2
before V
DD1
because the DIRx
and /OEx pins on the UT54ACS162245SLV are powered by
V
DD2
. If V
DD1
is powered on first, V
DD2
must be powered on
within 1 second of V
DD1
reaching 1.5V +/-5%. An elevated
V
DD1
supply current up to 150mA may occur when
V
DD1
> 1.5V+/5% and V
DD2
< 1.5V +/-5%.
VDD1
VDD2
DIR1
OE1
DIR2
OE2
PORTA
Enable/
Direction
Control
Logic
Enable/
Direction
Control
Logic
PORTB
CORE
POWER TABLE
Port B
3.3 Volts
3.3 Volts
2.5 Volts
Port A
2.5 Volts
3.3 Volts
2.5 Volts
OPERATION
Voltage Translator
Non Translating
Non Translating
Warm Spare
Once the UT54ACS162245SLV is powered up with
V
DD1
≥
V
DD2
, the application may place the device into “Warm
Spare” mode by driving EITHER supply to V
SS
+/- 0.25V with
a maximum 1kΩ impedance between V
DDx
and V
SS
. While in
Warm Spare, the device places all outputs into a high im-
pedeance state (see DC electrical parameters, Iws).
FUNCTION TABLE
ENABLE
OEx
L
L
H
DIRECTION
DIRx
L
H
X
OPERATION
B Data To A Bus
A Data To B Bus
Isolation
Cold Spare
The UT54ACS162245SLV places the device into “Cold Spare”
mode when BOTH supplies are set to V
SS
+/- 0.25V with a
maximum 1KΩ impedance between V
DDx
and V
SS
. While in
Cold Spare, the device places all outputs into a high impedeance
state (see DC electrical parameters, Ics).
Power Application Guidelines
For proper operation, connect power to all V
DD
pins and ground
all V
SS
pins (i.e., no floating V
DD
or V
SS
supply pins). If V
DD1
and V
DD2
are not powered up together, then V
DD2
should be
2
LOGIC DIAGRAM
DIR1
(1)
(48)
OE1
DIR2
(24)
(25)
OE2
1A1
(47)
(2)
1B1
2A1
(36)
(13)
2B1
1A2
(46)
(3)
1B2
2A2
(35)
(14)
2B2
1A3
(44)
(5)
1B3
2A3
(33)
(16)
2B3
3.3 V PORT
2.5V PORT
2.5V PORT
(6)
1A5
(41)
(8)
1A6
(40)
(9)
1A7
(38)
(11)
1A8
(37)
(12)
1B4
(17)
2A5
(30)
(19)
2A6
(29)
(20)
2A7
(27)
(22)
2A8
(26)
(23)
2B4
1B5
2B5
1B6
2B6
1B7
2B7
1B8
2B8
3
3.3 V PORT
1A4
(43)
2A4
(32)
OPERATIONAL ENVIRONMENT
1
PARAMETER
Total Dose
SEL Latchup
Neutron Fluence
(Note 2)
LIMIT
1.0E5
>113
1.0E14
UNITS
rad(Si)
MeV-cm
2
/mg
n/cm
2
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Not tested, inherent to CMOS technology.
ABSOLUTE MAXIMUM RATINGS
1
SYMBOL
V
I/O (Note 2)
V
DD1
V
DD2
T
STG
T
J (Note 3)
Θ
JC
I
I
P
D
PARAMETER
Voltage any pin
Supply voltage
Supply voltage
Storage Temperature range
Maximum junction temperature
Thermal resistance junction to case
DC input current
Maximum power dissipation
LIMIT (Mil only)
-.3 to V
DD1
+.3
-0.3 to 4.0
-0.3 to 4.0
-65 to +150
+150
20
±10
1
UNITS
V
V
V
°C
°C
°C/W
mA
W
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at
these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability and performance.
2. For Cold Spare mode (V
DD1
=VSS, V
DD2
=VSS), V
I/O
may be -0.3V to the maximum recommended operating level of V
DD1
+0.3V.
3. Maximum junction temperature may be increased to +175
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