August 2004
rev 2.0
3.3V Zero Delay Buffer
General Features
10 MHz to 133- MHz operating range, compatible
with CPU and PCI bus frequencies.
Zero input - output propagation delay.
Multiple low-skew outputs.
Output-output skew less than 250 ps.
Device-device skew less than 700 ps.
One input drives 9 outputs, grouped as 4 + 4
+ 1 (ASM5P2309A).
One input drives 5 outputs (ASM5P2305A).
®
ASMP5P2309A
ASMP5P2305A
133- MHz frequencies, and has higher drive than the -1
devices. All parts have on-chip PLL’s
that lock to an input
clock on the REF pin. The PLL feedback is on-chip and is
obtained from the CLKOUT pad.
The ASM5P2309A has two banks of four outputs each,
which can be controlled by the Select inputs as shown in
the Select Input Decoding Table. If all the output clocks are
not required, Bank B can be three-stated. The select input
also allows the input clock to be directly applied to the
outputs for chip and system testing purposes.
Multiple ASM5P2309A and ASM5P2305A devices can
accept the same input clock and distribute it. In this case
the skew between the outputs of the two devices is
guaranteed to be less than 700ps.
All outputs have less than 200 ps of cycle-to-cycle jitter.
0.35µ
CMOS
The input and output propagation delay is guaranteed to be
less than 250 ps, and the output to output skew is
guaranteed to be less than 250ps.
The ASM5P2309A and the ASM5P2305A are available in
two different configurations, as shown in the ordering
information table. The ASM5P23XXA-1 is the base part.
The ASM5P23XXA-1H is the high drive version of the -1
and its rise and fall times are much faster than -1 part.
packages
Less than 200 ps cycle-to-cycle jitter is compatible
with Pentium based systems.
Test Mode to bypass PLL (ASM5P2309A only,
refer Select Input Decoding Table).
Available in 16-pin, 150-mil SOIC, 4.4 mm
TSSOP,
and
150-mil
SSOP
(ASM5P2309A) or in 8-pin, 150- mil SOIC
package (ASM5P2305A).
3.3V
operation,
advanced
technology.
Functional Description
ASM5P2309A is a versatile, 3.3V zero-delay buffer
designed to distribute high-speed clocks. It accepts one
reference input and drives out nine low-skew clocks. It is
available in a 16-pin package. The ASM5P2305A is the
eight-pin version of the ASM5P2309A. It accepts one
reference input and drives out five low-skew clocks.
The -1H version of the ASM5P23XXA operates at up to
Block Diagram
REF
PLL
CLKOUT
REF
CLK1
PLL
MUX
CLKOUT
CLKA1
CLKA2
CLK2
CLK3
CLK4
S2
Select Input
Decoding
S1
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
ASM5P2305A
ASM5P2309A
Alliance Semiconductor
2575, Augustine Drive
Santa Clara, CA
Tel: 408.855.4900
Fax: 408.855.4999
www.alsc.com
Notice: The information in this document is subject to change without notice.
August 2004
rev 2.0
Select Input Decoding for ASM5P2309A
S2
0
0
1
1
S1
0
1
0
1
Clock A1 - A4
Three-state
Driven
Driven
Driven
Clock B1 - B4
Three-state
Three-state
Driven
Driven
CLKOUT
1
Driven
Driven
Driven
Driven
ASMP5P2309A
ASMP5P2305A
Output Source
PLL
PLL
Reference
PLL
PLL
Shut-Down
N
N
Y
N
Notes:
1. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to
change the skew between the reference and the output.
Zero Delay and Skew Control
All outputs should be uniformly loaded to achieve
Zero Delay between input and output. Since the
CLKOUT pin is the internal feedback to the PLL, its
relative loading can adjust the input-output delay.
For applications requiring zero input-output delay, all
outputs, including CLKOUT, must be equally loaded.
Even if CLKOUT is not used, it must have a
capacitive load equal to that on other outputs, for
obtaining zero-input-output delay.
Pin Configuration
REF
CLKA1
CLKA2
V
DD
1
2
3
4
5
6
7
8
16
15
14
13
CLKOUT
CLKA4
CLKA3
V
DD
GND
CLKB4
CLKB3
S1
GND
CLKB1
CLKB2
S2
ASM5P2309A
12
11
10
9
REF
CLK2
CLK1
GND
1
2
3
4
8
CLKOUT
CLK4
V
DD
ASM5P2305A
7
6
5
CLK3
3.3V Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
2 of 14
August 2004
rev 2.0
Pin Description for ASM5P2309A
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin Name
REF
2
ASM5P2309A
ASM5P2305A
Description
Input reference frequency, 5V tolerant input
Buffered clock output, bank A
Buffered clock output, bank A
3.3V supply
Ground
CLKA1
3
CLKA2
3
V
DD
GND
CLKB1
S2
4
S1
4
CLKB3
CLKB4
GND
V
DD
CLKA3
3
CLKA4
3
3
3
3
3
Buffered clock output, bank B
Buffered clock output, bank B
Select input, bit 2
Select input, bit 1
Buffered clock output, bank B
Buffered clock output, bank B
Ground
3.3V supply
Buffered clock output, bank A
Buffered clock output, bank A
Buffered output, internal feedback on this pin
CLKB2
3
CLKOUT
Pin Description for ASM5P2305A
Pin #
1
2
3
4
5
6
7
8
Pin Name
REF
2
CLK2
3
CLK1
3
GND
CLK3
3
V
DD
CLK4
3
Description
Input reference frequency, 5V-tolerant input
Buffered clock output
Buffered clock output
Ground
Buffered clock output
3.3V supply
Buffered clock output
Buffered clock output, internal feedback on this pin
CLKOUT
3
Notes:
2. Weak pull-down.
3. Weak pull-down on all outputs.
4. Weak pull-up on these inputs.
3.3V Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
3 of 14
August 2004
rev 2.0
Absolute Maximum Ratings
Parameter
Supply Voltage to Ground Potential
DC Input Voltage (Except REF)
DC Input Voltage (REF)
Storage Temperature
Max. Soldering Temperature (10 sec)
Junction Temperature
Static Discharge Voltage
(per MIL-STD-883, Method 3015)
Min
-0.5
-0.5
-0.5
-65
Max
+7.0
VDD + 0.5
7
+150
260
150
2000
ASM5P2309A
ASM5P2305A
Unit
V
V
V
°C
°C
°C
V
Note: These are stress ratings only and functional usage is not implied. Exposure to absolute maximum
ratings for prolonged periods can affect device reliability.
Operating Conditions for ASM5P2305A and ASM5P2309A - Commercial Temperature Devices
Parameter
V
DD
T
A
C
L
C
L
C
IN
Supply Voltage
Operating Temperature (Ambient Temperature)
Load Capacitance, below 100 MHz
Load Capacitance, from 100 MHz to 133 MHz
Input Capacitance
Description
Min
3.0
0
Max
3.6
70
30
10
7
Unit
V
°C
pF
pF
pF
3.3V Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
4 of 14
August 2004
rev 2.0
lectrical Characteristics for ASM5P2305A and ASM5P2309A - Commercial Temperature Devices
Parameter
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DD
Description
Input LOW Voltage
5
Input HIGH Voltage
Input LOW Current
Input HIGH Current
Output LOW Voltage
Output HIGH Voltage
Supply Current
6
5
ASM5P2309A
ASM5P2305A
Test Conditions
Min
Max
0.8
Unit
V
V
2.0
V
IN
= 0V
V
IN
= V
DD
I
OL
= 8mA (-1)
I
OH
= 12mA (-1H)
6
50.0
100.0
0.4
2.4
TBD
µA
µA
V
V
mA
I
OL
= -8mA (-1)
I
OH
= -12mA (-1H)
Unloaded outputs at 66.67 MHz,
SEL inputs at V
DD
S1 / S2 inputs are CMOS, TTL compatible inputs
–
The input must toggle somewhere between 0.8 and 2.0. We guarantee the limits of 0.8 and 2.0, but can't guarantee anything tighter than
that. As Vdd moves higher the toggle point will move higher, but will always stay below 2.0V. As Vdd moves lower, the toggle point will
move lower, but always stay higher than 0.8V. What the 2.0V MIN Vih specification means is that you put 2.0V or a higher voltage into the
device, and you will have a logic HIGH. If you put 0.8V or a lower voltage into the device, you will have a logic LOW ( Vil spec = 0.8V max).
It will toggle someplace in between 0.8V and 2.0V, but we don't guarantee exactly where, and the exact point will change depending upon
conditions. Characterization shows we toggle at 1.1V and 1.5V (showing a little hysteresis), everything is perfect. We meet spec, plus have
~ 300mV noise immunity on the low end and ~500mV noise immunity on the high side. Under nominal conditions, with no hysteresis, most
devices will toggle at about 1.5V for both high and low.
Switching Characteristics for ASM5P2305A-1 and ASM5P2309A-1 - Commercial Temperature Devices
7
Parameter
1/t
1
Description
Output Frequency
Duty Cycle
6
= (t
2
/ t
1
) * 100
t
3
t
4
t
5
t
6
t
7
t
J
t
LOCK
Output Rise Time
6
Output Fall Time
6
Test Conditions
30-pF load
10-pF load
Measured at 1.4V, F
OUT
= 66.67 MHz
Measured between 0.8V and 2.0V
Measured between 2.0V and 0.8V
All outputs equally loaded
Measured at V
DD
/2
Measured at V
DD
/2 on the CLKOUT pins of
the device
Measured at 66.67 MHz, loaded outputs
Stable power supply, valid clock presented
on REF pin
Min
10
10
40.0
Typ
Max
100
133.3 3
Unit
MHz
%
ns
ns
ps
ps
ps
ps
ms
50.0
60.0
2.50
2.50
250
Output-to-output skew
6
Delay, REF Rising Edge to
CLKOUT Rising Edge
6
Device-to-Device Skew
6
Cycle-to-cycle jitter
6
PLL Lock Time
6
0
0
±350
700
200
1.0
Notes:
5. REF input has a threshold voltage of VDD/2
6. Parameter is guaranteed by design and characterization. Not 100% tested in production
7. All parameters specified with loaded outputs.
3.3V Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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