Quad-SHARC
®
DSP Multiprocessor Family
AD14060/AD14060L
PERFORMANCE FEATURES
ADSP-21060 core processor ( × 4)
480 MFLOPS peak, 320 MFLOPS sustained
25 ns instruction rate, single-cycle
instruction execution—each of four processors
16 Mbit shared SRAM (internal to SHARCs)
4 gigawords addressable off-module memory
Twelve 40 Mbyte/s link ports (3 per SHARC)
Four 40 Mbit/s independent serial ports
(one from each SHARC)
One 40 Mbit/s common serial port
5 V and 3.3 V operation
32-bit single precision and 40-bit extended
precision IEEE floating point data formats, or
32-bit fixed point data format
IEEE JTAG Standard 1149.1 test access port and
on-chip emulation
FUNCTIONAL BLOCK DIAGRAM
CS
TIMEXP
LINK 1
LINK 3
LINK 4
IRQ
2–0
FLAG
2, 0
CS
TIMEXP
LINK 1
LINK 3
LINK 4
IRQ
2–0
FLAG
2, 0
SPORT 0
TCK, TMS, TRST
FLAG
1
FLAG
3
EBOOT,
LBOOT, BMS
EMU
CLKIN
RESET
(ID
2–0
= 1)
SHARC BUS (
ADDR31–0
,
DATA47–0
,
MS3-0
,
RD, WR, PAGE, ADRCLK,
,
SW, ACK, SBTS, HBR, HBG, REDY, BR
, RPBA, DMAR , DMAG )
6–1
1.2
1.2
EBOOT,
LBOOT, BMS
EMU
CLKIN
RESET
SPORT 0
TCK,TMS, TRST
FLAG
1
FLAG
3
EBOOT,
LBOOT, BMS
EMU
CLKIN
RESET
EBOOT,
LBOOT, BMS
EMU
CLKIN
RESET
SHARC_A
SHARC_B
(ID
2–0
= 2)
PACKAGING FEATURES
308-lead ceramic quad flatpack (CQFP)
2.05" (52 mm) body size
Cavity up or down, configurable
Low profile, 0.160" height
Hermetic
25 Mil (0.65 mm) lead pitch
29 grams (typical)
θ
JC
= 0.36°C/W
SHARC_D
SHARC_C
(ID
2–0
= 3)
CS
TIMEXP
LINK 1
LINK 3
LINK 4
IRQ
2–0
FLAG
2, 0
AD14060/AD14060L
Figure 1.
CS
TIMEXP
LINK 1
LINK 3
LINK 4
IRQ
2–0
FLAG
2, 0
CPA
(ID
2–0
= 4)
SPORT 1
TDO
LINK 0
LINK 2
LINK 5
TDI
LINK 0
LINK 2
LINK 5
TDO
GENERAL DESCRIPTION
The AD14060/AD14060L Quad-SHARC is the first in a family
of high performance DSP multiprocessor modules. The core of
the multiprocessor is the ADSP-21060 DSP microcomputer. The
AD14060/AD14060L has the highest performance-to-density
and lowest cost-to-performance ratios of any in its class. It is
ideal for applications requiring higher levels of performance
and/or functionality per unit area.
The AD14060/AD14060L takes advantage of the built-in
multiprocessing features of the ADSP-21060 to achieve
480 peak MFLOPS with a single chip type in a single package.
The on-chip SRAM of the DSPs provides 16 Mbits of on-
module shared SRAM. The complete shared bus (48 data,
32 address) is also brought off-module for interfacing with
expansion memory or other peripherals.
The ADSP-21060 link ports are interconnected to provide direct
communication among the four SHARCs, as well as high speed
off-module access. Internally, each SHARC has a direct link port
connection. Externally, each SHARC has a total of 120 Mbytes/s
link port bandwidth.
Multiprocessor performance is enhanced with embedded power
and ground planes, matched impedance interconnect, and
optimized signal routing lengths and separation. The fully
tested and ready-to-insert multiprocessor also significantly
reduces board space.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
SPORT 0
TCK,TMS, TRST
FLAG
1
FLAG
3
TDI
CPA
SPORT 1
00667-001
SPORT 0
TCK, TMS, TRST
FLAG
1
FLAG
3
TDO
CPA
SPORT 1
TDI
LINK 0
LINK 2
LINK 5
TDO
LINK 0
LINK 2
LINK 5
TDI
CPA
SPORT 1
AD14060/AD14060L
TABLE OF CONTENTS
Specifications..................................................................................... 3
Electrical Characteristics (3.3 V, 5 V Supply)............................ 3
Explanation of Test Levels........................................................... 4
Timing Specifications....................................................................... 5
Memory Read—Bus Master........................................................ 8
Memory Write—Bus Master ....................................................... 9
Synchronous Read/Write—Bus Master................................... 10
Synchronous Read/Write—Bus Slave ...................................... 12
Multiprocessor Bus Request and Host Bus Request .............. 13
Asynchronous Read/Write—Host to AD14060/AD14060L. 15
Three-State Timing—Bus Master, Bus Slave, HBR, SBTS ..... 17
DMA Handshake........................................................................ 18
Absolute Maximum Ratings.......................................................... 27
ESD Caution................................................................................ 27
Pin Configuration and Function Descriptions........................... 28
Pin Function Descriptions ........................................................ 30
Detailed Description ...................................................................... 34
Architectural Features................................................................ 34
Shared Memory Multiprocessing ............................................. 34
Off-Module Memory and Peripherals Interface .................... 36
Link Port I/O............................................................................... 38
Serial Ports .................................................................................. 38
Program Booting ........................................................................ 38
Host Processor Interface ........................................................... 39
Direct Memory Access (DMA) Controller ............................. 39
Applications..................................................................................... 40
Development Tools .................................................................... 40
Quad-SHARC Development Board......................................... 40
Other Package Details................................................................ 40
Target Board Connector for Emulator Probe......................... 40
Output Drive Currents .............................................................. 42
Power Dissipation ...................................................................... 42
Test Conditions........................................................................... 43
Assembly Recommendations.................................................... 45
PCB Layout Guidelines.............................................................. 46
Mechanical Characteristics ....................................................... 47
Additional Information ............................................................. 47
Outline Dimensions ....................................................................... 48
Ordering Guide .......................................................................... 48
REVISION HISTORY
12/04—Rev. A to Rev. B
Format Updated..................................................................Universal
Changes to Specifications Section.................................................. 3
Changes to Development Tools Section ...................................... 40
Changes to Target Board for Emulator Probe Section .............. 40
Changes to Figure 27...................................................................... 42
Updated Outline Dimensions ....................................................... 48
Changes to Ordering Guide .......................................................... 48
10/97—Rev. 0 to Rev. A
4/97—Revision 0: Initial Version
Rev. B | Page 2 of 48
AD14060/AD14060L
SPECIFICATIONS
Table 1. Recommended Operating Conditions
Parameter
V
DD
T
CASE
Supply Voltage (5 V)
Supply Voltage (3.3 V)
Case Operating Temperature
Min
4.75
3.15
−40
B Grade
Max
5.25
3.6
+100
Min
4.75
3.15
0
K Grade
Max
5.25
3.6
+85
Unit
V
V
°C
ELECTRICAL CHARACTERISTICS (3.3 V, 5 V SUPPLY)
Table 2.
Parameter
V
IH1
V
IH2
V
IL
V
OH
V
OL
I
IH
I
IL
I
ILP
I
ILPX4
I
OZH
I
OZL
I
OZHP
I
OZLC
I
OZLA
I
OZLAR
I
OZLS
I
OZLSX4
I
DDIN
I
DDIDLE
C
IN
High Level Input Voltage
High Level Input Voltage
2
Low Level Input Voltage
1
,
2
High Level Output Voltage
3, 4
Low Level Output Voltage
3
,
4
High Level Input Current
5, 6, 7
Low Level Input Current
5
Low Level Input Current
6
Low Level Input Current
Three-State Leakage Current
8, 9, 10, 11
Three-State Leakage Current
8
, 12
Three-State Leakage Current
12
Three-State Leakage Current
13
Three-State Leakage Current
14
Three-State Leakage Current
10
Three-State Leakage Current
9
Three-State Leakage Current
Supply Current (Internal)
15
Supply Current (Idle)
16
Input Capacitance
17, 18
11
7
1
Case
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
Test
Level
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
IV
I
V
Test Condition
@ V
DD
= max
@ V
DD
= max
@ V
DD
= min
@ V
DD
= min, I
OH
= −2.0 mA
@ V
DD
= min, I
OL
= 4.0 mA
4
4
Min
2.0
2.2
4.1
5V
Typ Max
V
DD
+ 0.5
V
DD
+ 0.5
0.8
0.4
10
10
150
600
10
10
350
1.5
350
4.2
150
600
1.4
15
2.92
800
Min
2.0
2.2
2.4
3.3 V
Typ Max
V
DD
+ 0.5
V
DD
+ 0.5
0.8
0.4
10
10
150
600
10
10
350
1.5
350
4.2
150
600
1.0
15
2.2
760
Unit
V
V
V
V
V
µA
µA
µA
µA
µA
µA
µA
mA
µA
mA
µA
µA
A
mA
pF
@ V
DD
= max, V
IN
= V
DD
max
@ V
DD
= max, V
IN
= 0 V
@ V
DD
= max, V
IN
= 0 V
@ V
DD
= max, V
IN
= 0 V
@ V
DD
= max, V
IN
= V
DD
max
@ V
DD
= max, V
IN
= 0 V
@ V
DD
= max, V
IN
= V
DD
max
@ V
DD
= max, V
IN
= 0 V
@ V
DD
= max,
V
IN
= 1.5 V (5 V), 2 V (3.3 V)
@ V
DD
= max, V
IN
= 0 V
@ V
DD
= max, V
IN
= 0 V
@ V
DD
= max, V
IN
= 0 V
t
CK
= 25 ns, V
DD
= max
V
DD
= max
1
Applies to input and bidirectional pins: DATA
47-0
, ADDR
31-0
, RD, WR, SW, ACK, STBS, IRQy
2-0
, FLAGy0, FLAG1, FLAGy2, HBG, CSy, DMAR1, DMAR2, BR
6-1
, RPBA, CPAy, TFS0,
TFSy1, RFS0, RFSy1, LyxDAT
3-0
, LyxCLK, LyxACK, EBOOTA, LBOOTA, EBOOTBCD, LBOOTBCD, BMSA, BMSBCD, TMS, TDI, TCK, HBR, DR0, DRy1, TCLK0, TCLKy1, RCLK0,
RCLKy1.
2
Applies to input pins: CLKIN, RESET, TRST.
3
Applies to output and bidirectional pins: DATA
47-0
, ADDR
31-0
, MS
3-0
, RD, WR, PAGE, ADRCLK, SW, ACK, FLAGy0, FLAG1, FLAGy2, TIMEXPy, HBG, REDY, DMAG1, DMAG2,
BR
6-1
, CPAy, DTO, DTy1, TCLK0, TCLKy1, RCLK0, RCLKy1, TFS0, TFSy1, RFS0, RFSy1, LyxDAT
3-0
, LyxCLK, LyxACK, BMSA, BMSBCD, TDO, EMU.
4
See the Output Drive Currents section for typical drive current capabilities.
5
Applies to input pins: STBS, IRQy
2-0
, HBR, CSy, DMAR1, DMAR2, RPBA, EBOOTA, LBOOTA, EBOOTBCD, LBOOTBCD, CLKIN, RESET, TCK.
6
Applies to input pins with internal pull-ups: DR0, DRy1, TDI.
7
Applies to bused input pins with internal pull-ups: TRST, TMS.
8
Applies to three-statable pins: DATA
47-0
, ADDR
31-0
, MS
3-0
, RD, WR, PAGE, ADRCLK, SW, ACK, FLAGy0, FLAG1, FLAGy2, REDY, HBG, DMAG1, DMAG2, BMSA, BMSBCD, TDO,
EMU. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID
2-0
= 001 and another ADSP-2106x is not requesting bus
mastership. HBG and EMU are not tested for leakage current.)
9
Applies to three-statable pins with internal pull-ups: DTy1, TCLKy1, RCLKy1.
10
Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID
2-0
= 001 and another
ADSP-2106x is not requesting bus mastership.)
11
Applies to bused three-statable pins with internal pull-ups: DT0, TCLK0, RCLK0.
12
Applies to three-statable pins with internal pull-downs: LyxDAT
3-0
, LyxCLK, LyxACK.
13
Applies to CPAy pin.
14
Applies to ACK pin, when the keeper latch is enabled.
15
Applies to V
DD
pins. Conditions of operation: each processor is executing radix-2 FFT butterfly with instruction in cache, one data operand is fetched from each
internal memory block, and one DMA transfer is occurring from/to internal memory at t
CK
= 25 ns.
16
Applies to V
DD
pins. Idle denotes AD14060/AD14060L state during execution of IDLE instruction.
17
Applies to all signal pins.
18
Guaranteed, but not tested.
Rev. B | Page 3 of 48
AD14060/AD14060L
EXPLANATION OF TEST LEVELS
Test
I
II
III
IV
V
VI
Level
100% production tested.
1
100% production tested at 25°C, and sample tested at
specified temperatures.
Sample tested only.
Parameter is guaranteed by design and analysis, and
characterization testing on discrete SHARCs.
Parameter is typical value only.
All devices are 100% production tested at 25°C, and
sample tested at temperature extremes.
1
Link and serial ports: All are 100% tested at die level prior to assembly. All are
100% ac tested at module level; Link 4 and Serial 0 are also dc tested at the
module level. See the Timing Specifications section.
Rev. B | Page 4 of 48
AD14060/AD14060L
TIMING SPECIFICATIONS
This data sheet represents production-released specifications
for the AD14060 (5 V), and for the AD14060L (3.3 V). The
ADSP-21060 die components are 100% tested, and the
assembled AD14060/AD14060L units are again extensively
tested at speed and across temperature. Parametric limits were
established from the ADSP-21060 characterization followed by
further design and analysis of the AD14060/AD14060L package
characteristics.
The specifications are based on a CLKIN frequency of 40 MHz
(t
CK
= 25 ns). The DT derating allows specifications at other
CLKIN frequencies (within the minimum to maximum range
of the t
CK
specification; see Table 3). DT is the difference
between the actual CLKIN period and a CLKIN period of 25 ns:
DT
=
t
CK
− 25 ns
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
Table 3. Clock Input
Parameter
Clock Input
Timing Requirements:
t
CK
CLKIN Period
t
CKL
CLKIN Width Low
t
CKH
CLKIN Width High
t
CKRF
CLKIN Rise/Fall (0.4 V to 2.0 V)
Min
40 MHz (5 V)
Max
40 MHz (3.3 V)
Min
Max
Unit
reflect statistical variations and worst cases. Consequently, one
cannot meaningfully add parameters to derive longer times.
Switching Characteristics
specify how the processor changes its
signals. The user has no control over this timing—circuitry
external to the processor must be designed for compatibility
with these signal characteristics. Switching characteristics
specify what the processor does in a given circumstance. The
user can also use switching characteristics to ensure that any
timing requirement of a device connected to the processor
(such as memory) is satisfied.
Timing Requirements
apply to signals that are controlled by
circuitry external to the processor, such as the data input for a
read operation. Timing requirements guarantee that the
processor operates correctly with other devices.
(O/D) = Open Drain
(A/D) = Active Drive
25
7
5
100
25
9.5
5
100
3
3
ns
ns
ns
ns
t
CK
00667-011
CLKIN
t
CKH
t
CKL
Figure 2. Clock Input
Rev. B | Page 5 of 48
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